Taint injection and tracking

ABSTRACT

An embodiment or embodiments of an electronic device can comprise an input interface and a hardware component coupled to the input interface. The input interface can be operable to receive a plurality of taint indicators corresponding to at least one of a plurality of taints indicative of potential security risk which are injected from at least one of a plurality of resources. The hardware component can be operable to track the plurality of taints.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is related to and claims the benefit of theearliest available effective filing date(s) from the following listedapplication(s) (the “Related Applications”) (e.g., claims earliestavailable priority dates for other than provisional patent applicationsor claims benefits under 35 USC §119(e) for provisional patentapplications, for any and all parent, grandparent, great-grandparent,etc. applications of the Related Application(s)).

RELATED APPLICATIONS

For purposes of the United States Patent and Trademark Office (USPTO)extra-statutory requirements (described more fully below), the presentapplication is:

-   -   1. For purposes of the USPTO extra-statutory requirements, the        present application constitutes a continuation-in-part of U.S.        patent application Ser. No. 13/136,024 entitled CONTROL FLOW        INTEGRITY filed on Jul. 19, 2011, and naming Andrew F. Glew,        Daniel A. Gerrity, and Clarence T. Tegreene as inventors, which        is currently co-pending, or is an application of which a        currently co-pending application is entitled to the benefit of        the filing date.    -   2. For purposes of the USPTO extra-statutory requirements, the        present application constitutes a continuation-in-part of U.S.        patent application Ser. No. 13/136,400 entitled ENCRYPTED MEMORY        filed on Jul. 29, 2011, and naming Andrew F. Glew, Daniel A.        Gerrity, and Clarence T. Tegreene as inventors, which is        currently co-pending, or is an application of which a currently        co-pending application is entitled to the benefit of the filing        date.    -   3. For purposes of the USPTO extra-statutory requirements, the        present application constitutes a continuation-in-part of U.S.        patent application Ser. No. 13/136,401 entitled FINE-GRAINED        SECURITY IN FEDERATED DATA SETS filed on Jul. 29, 2011, and        naming Andrew F. Glew, Daniel A. Gerrity, and Clarence T.        Tegreene as inventors, which is currently co-pending, or is an        application of which a currently co-pending application is        entitled to the benefit of the filing date.    -   4. For purposes of the USPTO extra-statutory requirements, the        present application constitutes a continuation-in-part of U.S.        patent application Ser. No. 13/136,666 entitled SECURITY        PERIMETER filed on Aug. 4, 2011, and naming Andrew F. Glew,        Daniel A. Gerrity, and Clarence T. Tegreene as inventors, which        is currently co-pending, or is an application of which a        currently co-pending application is entitled to the benefit of        the filing date.    -   5. For purposes of the USPTO extra-statutory requirements, the        present application constitutes a continuation-in-part of U.S.        patent application Ser. No. 13/136,670 entitled PROCESSOR        OPERABLE TO ENSURE CODE INTEGRITY filed on Aug. 4, 2011, and        naming Andrew F. Glew, Daniel A. Gerrity, and Clarence T.        Tegreene as inventors, which is currently co-pending, or is an        application of which a currently co-pending application is        entitled to the benefit of the filing date.    -   6. For purposes of the USPTO extra-statutory requirements, the        present application constitutes a continuation-in-part of U.S.        patent application Ser. No. 13/199,368 entitled INTRUSTION        DETECTION USING TAINT ACCUMULATION filed on Aug. 26, 2011, and        naming Andrew F. Glew, Daniel A. Gerrity, and Clarence T.        Tegreene as inventors, which is currently co-pending, or is an        application of which a currently co-pending application is        entitled to the benefit of the filing date.    -   7. For purposes of the USPTO extra-statutory requirements, the        present application constitutes a continuation-in-part of U.S.        patent application Ser. No. 13/200,547 entitled INTRUSTION SET        ADAPTED FOR SECURITY RISK MONITORING filed on Sep. 24, 2011, and        naming Andrew F. Glew, Daniel A. Gerrity, and Clarence T.        Tegreene as inventors, which is currently co-pending, or is an        application of which a currently co-pending application is        entitled to the benefit of the filing date.    -   8. For purposes of the USPTO extra-statutory requirements, the        present application constitutes a continuation-in-part of U.S.        patent application Ser. No. 13/200,557 entitled RESOURCE        ALLOCATION USING ENTITLEMENTS filed on Sep. 24, 2011, and naming        Andrew F. Glew, Daniel A. Gerrity, and Clarence T. Tegreene as        inventors, which is currently co-pending, or is an application        of which a currently co-pending application is entitled to the        benefit of the filing date.    -   9. For purposes of the USPTO extra-statutory requirements, the        present application constitutes a continuation-in-part of U.S.        patent application Ser. No. 13/200,550 entitled RESOURCE        ALLOCATION USING A LIBRARY WITH ENTITLEMENT filed on Sep. 24,        2011, and naming Andrew F. Glew, Daniel A. Gerrity, and        Clarence T. Tegreene as inventors, which is currently        co-pending, or is an application of which a currently co-pending        application is entitled to the benefit of the filing date.    -   10. For purposes of the USPTO extra-statutory requirements, the        present application constitutes a continuation-in-part of U.S.        patent application Ser. No. 13/200,556 entitled RESOURCE        ALLOCATION WITH ENTITLEMENT HINTS filed on Sep. 24, 2011, and        naming Andrew F. Glew, Daniel A. Gerrity, and Clarence T.        Tegreene as inventors, which is currently co-pending, or is an        application of which a currently co-pending application is        entitled to the benefit of the filing date.    -   11. For purposes of the USPTO extra-statutory requirements, the        present application constitutes a continuation-in-part of U.S.        patent application Ser. No. 13/317,834 entitled ENTITLEMENT        VECTOR WITH RESOURCE AND/OR CAPABILITIES FIELDS filed on Oct.        28, 2011, and naming Andrew F. Glew, Daniel A. Gerrity, and        Clarence T. Tegreene as inventors, which is currently        co-pending, or is an application of which a currently co-pending        application is entitled to the benefit of the filing date.    -   12. For purposes of the USPTO extra-statutory requirements, the        present application constitutes a continuation-in-part of U.S.        patent application Ser. No. 13/317,826 entitled ENTITLEMENT        VECTOR FOR MANAGING RESOURCE ALLOCATION filed on Oct. 28, 2011,        and naming Andrew F. Glew, Daniel A. Gerrity, and Clarence T.        Tegreene as inventors, which is currently co-pending, or is an        application of which a currently co-pending application is        entitled to the benefit of the filing date.    -   13. For purposes of the USPTO extra-statutory requirements, the        present application constitutes a continuation-in-part of U.S.        patent application Ser. No. 13/317,825 entitled TAINT VECTOR        LOCATIONS AND GRANULARITY filed on Oct. 28, 2011, and naming        Andrew F. Glew, Daniel A. Gerrity, and Clarence T. Tegreene as        inventors, which is currently co-pending, or is an application        of which a currently co-pending application is entitled to the        benefit of the filing date.    -   14. For purposes of the USPTO extra-statutory requirements, the        present application constitutes a continuation-in-part of U.S.        patent application Ser. No. 13/317,980 entitled CONDITIONAL        SECURITY RESPONSE USING TAINT VECTOR MONITORING filed on Oct.        31, 2011, and naming Andrew F. Glew, Daniel A. Gerrity, and        Clarence T. Tegreene as inventors, which is currently        co-pending, or is an application of which a currently co-pending        application is entitled to the benefit of the filing date.

The United States Patent and Trademark Office (USPTO) has published anotice to the effect that the USPTO's computer programs require thatpatent applicants reference both a serial number and indicate whether anapplication is a continuation or continuation in part. Stephen G. Kunin,Benefit of Prior-Filed Application, USPTO Electronic Official Gazette,Mar. 18, 2003. The present applicant entity has provided a specificreference to the application(s) from which priority is being claimed asrecited by statute. Applicant entity understands that the statute isunambiguous in its specific reference language and does not requireeither a serial number or any characterization such as “continuation” or“continuation-in-part.” Notwithstanding the foregoing, applicant entityunderstands that the USPTO's computer programs have certain data entryrequirements, and hence applicant entity is designating the presentapplication as a continuation in part of its parent applications, butexpressly points out that such designations are not to be construed inany way as any type of commentary and/or admission as to whether or notthe present application contains any new matter in addition to thematter of its parent application(s).

All subject matter of the Related Applications and of any and allparent, grandparent, great-grandparent, etc. applications of the RelatedApplications is incorporated herein by reference to the extent suchsubject matter is not inconsistent herewith.

BACKGROUND

Malicious software, also called malware, refers to programming (code,scripts, active content, and other software) designed to disrupt or denyoperation, gather information to violate privacy or exploitation, gainunauthorized access to system resources, and enable other abusivebehavior. The expression is a general term used by computerprofessionals to mean a variety of forms of hostile, intrusive, orannoying software or program code.

Malware includes various software including computer viruses, worms,Trojan horses, spyware, dishonest adware, scareware, crimeware,rootkits, and other malicious and unwanted software or program, and isconsidered to be malware based on the perceived intent of the creatorrather than any particular features. In legal terms, malware issometimes termed as a “computer contaminant,” for example in the legalcodes of U.S. states such as California.

SUMMARY

An embodiment or embodiments of an electronic device can comprise aninput interface and a hardware component coupled to the input interface.The input interface can be operable to receive a plurality of taintindicators corresponding to at least one of a plurality of taintsindicative of potential security risk which are injected from at leastone of a plurality of resources. The hardware component can be operableto track the plurality of taints.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention relating to both structure and method ofoperation may best be understood by referring to the followingdescription and accompanying drawings:

FIGS. 1A, 1B, 1C, 1D, and 1E are respectively, first, second, third,fourth, and fifth schematic block diagrams, and a graphical datadescription depict embodiments of a electronic device adapted to managesecurity risk by tracking taints and taint indications, and respond bytrapping;

FIG. 1F is a graphical data description showing an aspect of operationof the electronic device;

FIGS. 1G and 1H are data structure diagrams illustrating exampleembodiments of taint vector;

FIGS. 2A through 2U are schematic flow diagrams showing an embodiment orembodiments of a method operable in a computing device adapted to managesecurity risk by tracking taints and taint indications, and respond bytrapping;

FIGS. 3A, 3B, and 3C are schematic block diagrams showing embodiments ofa computer program product adapted to manage security risk by trackingtaints and taint indications, and respond by trapping;

FIGS. 4A, 4B, and 4C are schematic block diagrams illustratingembodiments of a electronic device adapted to manage security risk bytracking taints and taint indications, and respond by trapping;

FIG. 5 is a schematic block diagram that shows an example embodiment ofa computing device in which embodiments may be implemented; and

FIG. 6 is a schematic block diagram depicting an example embodiment of ageneral-purpose computing system in which embodiments may beimplemented.

DETAILED DESCRIPTION

In various embodiments, computer systems and associated methods can beconfigured to include one or more of several improvements thatfacilitate security. One aspect can be accumulation of taint indicatorsto distinguish between safe and potentially unsafe data received fromsafe and potentially unsafe sources. Another aspect is specification andusage of a taint vector to enable monitoring and tracking of a largenumber of resources and conditions or a wide variety of types withoutburdening the system and operations with a significant amount ofhardware and complexity.

Security in existing networks, systems, and computers is coarse-graineddue to large granularity of native code, for example imposed by the 4kilobyte (kb) size of a virtual memory page. Security is sought in anenvironment characterized by running of applications that share datawith other entities. Security is coarse-grained in that memory blockscan be individually protected. For binary code or machine code, the 4 kbgranularity encompasses a large amount of data in comparison to thetypical 10 or 12-bit size of machine code words for which individualprotection may be sought.

Another security technique can be to assign data to a particular virtualmachine, which is even more coarse-grained. For example, if security issought in the context of a browser not known to be secure, the browsercan be assigned a virtual machine that runs only the browser. A virtualmachine can encompass more than a CPU alone and include other componentsand devices such as motherboard I/O devices. The virtual machine thuscan be much larger than the 4 kb granularity of memory blocks.

Security can also be sought in software or interpretive environments,for example using Java byte code or C-sharp byte code, which can be morefine-grained but at the cost of much slower performance. An interpretercan support any protection desired, even down to individual bits but ismuch slower than the machine code level. Performance can be acceleratedonly by more coarse-grained checking.

What is desired is fine-grained security with suitable speedperformance. Fine-grained security is directed toward protecting memoryin fine-grained pieces.

Fine-grained security can support resource allocation and resourcescheduling, and can be supporting technology for hardware scheduling,virtual memory. Fine-grained security facilitates, for example, forrunning applications on a computer controlled and owned by anotherentity.

Various techniques can be used to identify the memory items to beprotected including pointers such as a pointer to an object or metadataassociated with a pointer, offsets, addresses, and the like.

An example fine-grained security paradigm can use metadata associatedwith a pointer that identifies a lower bound, and upper bound, andpermissions. The pointer can be enabled to point to particular objectsor even to any position within an object. Metadata can specifypermissions including memory locations to which data can be written,when program code is allowed to execute, how long writing is allowed,and the like. Permissions can be associated with data objects, forexample assigning a pointer to an object and, using permissions,allowing only methods belonging to that object to access the object.Another example of permissions can enable access to data, but only forspecified purposes, for instance to enable a first running of an objectand access allowed to only part of a routine, while preventing access byothers. In another example, a particular method can be permitted to runa limited number of times or just one time, and can prevent subsequentaccess to data when the data has been previously exposed to anauthorized reader.

Permissions can implement a concept of poisoning. For example, a usercan enter a name into a text field and mark a poisoned bit that preventssubsequent branching or subroutine return (e.g. the software managingthe form can set a poison or taint bit). The poisoned bit can functionas a dirty bit which indicates whether an item such as an object,memory, or other resource is dirty, which prevents predeterminedpurposes or actions to the item, for example preventing actions appliedto a data block or object, such as not allowing return (e.g. notallowing execution of the data bytes entered by the user as code, suchas is done by stack smashing attacks) In some implementations, thepoisoned (or tainted) bit may be used to track which sensor providedwhich data, for example, for security reasons, for billing reasons, orfor any other suitable reasons.

An illustrative computer system can be configured for fine-grainedsecurity as supporting infrastructure in a concept of federated sharingand federated data sets. Sensor fusion involves fusing of data and datasets in numerical aspects and permissions aspects, wherein data and datasets are fused in conditions of a first entity owning or controlling afirst sensor and a second entity a second sensor.

Fine-grained security can be implemented in an infrastructure can beimplemented in an architecture including servers and clients. Forexample, gaming code servers and gaming console clients can interact byrunning program code that executes in part on machines controlled by theserver and in part on machines controlled by the client. Fine-grainedsecurity enables the interaction to be mutually trusted by both sides.

Fine-grained security can be configured to exploit existinginfrastructure aspects such as the Trusted Platform Module (TPM) whichis installed in computer systems somewhat universally but little used inpractice. TPM generally includes secure storage for keys but little orno security logic, certainly not enough to implement fine grainsecurity.

In some embodiments, a servers and clients architecture can implementfine-grained security using one or more server downloaded modules. Forexample, a gaming code server can transfer a server downloaded modulethat executes on a client. Fine-grained security can be configured toallow downloaded modules to execute securely, for example to ensureisolation in software, and further configured to prevent physicalattacks for example via a device such as a logic analyzer on the busreading sensitive information.

Some system embodiments which support fine-grained security can beactivated at boot-strap loading of a computer, for example via microcodeexecuting in the processor. At boot-strap loading, TPM fine-grainedsecurity can perform various security operations such as inspectingsoftware version and possibly microcode, ensuring viability of software,for example by creating and applying a hash to each level of code(microcode, firmware, software, and the like), checking againstpreviously run code, signing-off on viability if warranted, and printinga signature of executing code to enable determination of trust.

Fine-grained security operations can further include building orcreating a chain of trust, checking each part of operation beginningwith TPM, then checking security during operating system functions,downloading of modules, and execution of procedures. In an exampleconfiguration, fine-grained security can perform checks of operationsystem functions which, to the first order, control all operations.

An example of chain of trust can begin with trust of an operating system(for example by an association such as Motion Picture Association ofAmerica (MPAA), International Game Developers Association (IGDA), andthe like). If the operating system is certified and fine-grainedsecurity operable under the certified operating system ensures that thesystem is not hacked, the chain of trust is established since theoperating system prevents user code from accessing downloadable code.

Weaknesses of the chain of trust can be that the process is too linearand easy to break since a single-point of failure breaks trust. Chain oftrust also has problems ensuring privacy.

An extension that can improve chain of trust is a late-secure boot whichis run later than a typical bootstrap load and can involve securitychecking in an operating system that is not yet trusted. At running ofthe late-secure boot, a security initialization is run which startssecurity process booting in a system that is already running.

A more secure concept of security can be a web of trust. The web oftrust can have multiple trust levels which hand trust to the operatingsystem. At each trust level, software can validate code in a stack ofcode to establish trust. In the web of trust, a failure at some pointcan be rechecked according to one or more alternate paths (e.g. in someimplementations, byzantine agreement protocols can be used which form aset of protocols to establish trusty. The operating system can usepathfinding or agglomerated trust protocols to analyze trust at eachlevel to enable multiple levels or types of trust validation.

Intrusion detection can be an aspect of fine-grained security.

Intrusion detection can use the concept of poisoning. Poisoning can beused for protection, for example in the case of sensor data or a sensorcontrolled by an untrusted entity. One or more bits can be allocated toidentify aspects of the target sensor and data. Poisoning can bedata-defined or entity-defined.

A system can enforce security via accumulation which can be used toquantify poisoning, for example by accumulating multiple indicators oflack of safety or “dirtiness.” Accumulation can be operable toaccumulate on a per-location basis, per-data basis, overall, or anyselected combination. Accumulation can be used to quantify whether datafrom a particular source or entity can be trusted, rather than to detectsecurity attacks per se.

A taint technique can be used to distinguish between safe andpotentially unsafe data received from safe and potentially unsafesources. The term “taint” can be defined as potentially unsafe data ordata received from a potentially unsafe source. Unsafe data and/orsources are untrusted as potentially dangerous, malicious, or suspectaccording to a predetermined security policy. In general, “taint” neednot be purely negative (e.g. one might taint sensor data so as to knowwhich provider of sensor data should be given credit if used). Securitycriteria of tainting can be specified independently for variousapplications, conditions, and/or implementations ranging, for example,from a source, data, and/or resources via which the data is transmittedthat are not known to be completely trusted to those known to havepositive confirmation of ill-intent, malice, or compromised securityattributes. In some implementations, analysis of the data itself maycontribute to taint characterization.

Accumulation enables analysis of a particular sensor which is notuntrusted as fundamentally faulty or inherently dishonest but ratherimperfect to some degree, for example with a signal to noise ratio thatallows some errors. Thus, data may be trusted overall or over time, butpossibly an individual bit may not be trusted. Accumulators can gathertaints up to a predetermined threshold, after which an action may betaken. A taint can arise from software, can be forwarded from anoriginal source, may result from an attacker attempting to break into aweb browser, or may be “operational” for null pointers, buffer overruns,and other faults. In various embodiments and/or conditions, accumulationmay be per source, overall, or both. One or more bits can be accumulatedper untrusted source. The accumulation can be configured to be subjectto various selected algorithms, for example power law, race functions,and the like.

In a power law algorithm, the frequency of a security risk event ispresumed to vary as a power of some attribute of the event. The powerlaw relationship is believed to apply to distributions of a wide varietyof physical, biological, and man-made phenomena such as sizes ofgeophysical and weather events, neuronal activity patterns, frequenciesof words in various languages, and many other examples.

In a race function, a security risk event is presumed to followexponential or geometric change, either growth or decay, wherein therate of change of a mathematical function is proportional to thefunction's current value.

An accumulator can be configured using any suitable arithmetic or logicelement, and can accumulate data in any suitable manner, such as acounter or bit per source, a bit per accumulator. The accumulator can beconfigured to address information from different sources and atdifferent times in selected distinctive manners. For example, anaccumulator can be set so that 99% correct data is sufficient and aclean bit indicated despite occasional errors, while data from anothersource may be known to be valid only 65% of the time wherein a selectedalgorithm can be run, for example power law, race function, or the like,to determine validity.

On the specific case of sensor, some errors occur because sensors aren'tperfect, a signal to noise characteristic is present so some errors willoccur, even in the case that data is usually correct 99% of the time.Thus, the data can be generally trusted cumulatively with some level oftrust to individual bits. An entity that is not trusted will haveoutlier in terms of error rate, not criteria per error rates. In somecircumstances one definition of trusted/untrusted can be specified ortracking can be done on source and data basis. In a federated system,tracking can be on the basis of the sensor of one entity against anotherentity.

Various other accumulator examples can be implemented. A counter peraffiliation can be defined wherein a low level is merged up to a higherlevel. Pathways to a system can track sources of data through a systemsuch as by running data through a specified pathway through a“validator,” a software program or hardware logic used to check thevalidity of multiple taint indicators in terms of security risk. A2-4-bit counter can be used to track one-bit per source or a counter persource.

Tainting can be performed on a one-bit basis for a small number ofsources which can be federated down to whatever sources are desired. Anaccumulator can be configured to count the number of taints, such as thetaints per memory unit (per byte for example). Statistics can beperformed on any suitable taint counter—a counter per bit, 2-bitcounter, 4-bit counter and the like. Examples of taints and/or events tofilter can be used for taint monitoring and creation of a trust profileand include: instructions tainted, the number of tainted instructions,the number of instructions written as a result, the number of data loadsand stores, the number of data memory accesses, outputs, calls/returns,branches (for control flow), integer overflows, network I/O, and thelike. An integer overflow can be handled as a taint. Integer overflowsoccur frequently and can be legitimate about half the time, and thus acondition indicating possible error but by no means certainty of error.

Monitoring of network I/O is useful for detecting when a virus attemptsto call home. The system can trap to software if any specified taintoccurs, a simple reaction for any suspicious event.

Accumulators can be used to build a trust profile over time, such as byusing taint information as raw data for creating the trust profile. Thetrust profile can be used to lower and raise the trust level over time,and to make subsequent decisions. For example, a bit or counter candecay over time to balance race with accumulation.

Any suitable comparisons can be defined for particular conditions. In anillustration, a trust profile of an I/O process can be built over time.In a simple control scheme, a high-risk operation can be monitored sothat if the number of taints is greater than a predetermined threshold,I/O can be blocked. Over time, the count can be decremented to accountfor spurious events.

Suspicious activities can be monitored using comparisons, for exampleusing a counter or a single-bit designating suspicious events. Examplesof suspicious activities can include null pointer references which arenot always intentional or malware, buffer overruns/overflows which areusually untrusted, repeated attempts to access a key, and the like.

Comparisons can be used to efficiently track suspicious activities,particularly in conditions that complex statistical analysis isunavailable or unwarranted.

A taint vector, operable as an intrusion detection system, can becreated for tracking multiple events or conditions. An example taintvector can comprise 16-64 bits corresponding to associated sources,events, conditions, and/or suspicious activities. Each taint vector of acomposite vector may correspond to a source of data or a type ofactivity. Taint vectors enable monitoring and tracking of a large numberof resources and conditions or a wide variety of types without burdeningthe system and operations with a significant amount of hardware andcomplexity. The taint vector can include a various decay optionstailored to the particular information monitored. For example, the taintvector can decay after a certain number of operations to avoidtriggering on outlying events. Possibly schemes for implementing decaycan include: 1) increment/decrement using a single vector which isincrementing and decrementing is performed on the same vector, 2)copying the vector to memory periodically to maintain on old versionwhile continuously incrementing and decrementing to enable restorationof the old version subsequent to reacting to an invalid or errorcondition, and 3) impose a decay that is a race of decay versusaccumulation.

A taint vector can be configured to introduce a new class or type ofsecurity element, not taints but rather suspicious activities includingnull pointers and buffer overflows. Suspicious events are taints or canbe treated and propagated like taints.

The taint vector can be tailored to monitor various comparisonsincluding, for example: are any elements greater than threshold, are allgreater than threshold, is the sum of all or some elements greater thanthreshold, is the sum greater than an intermediate value, and the like.The system can trap if the taint vector meets predetermined conditions.

The taint vector can be considered an accumulator of faux pas, forexample null pointer references, attempts to access a secure part of theCPU, buffer overruns (a common hacking technique). The taint vector canbe used to monitor events or conditions that are not necessarily attacksor failures but may be innocent or coincidental, but originates in aregion that raises suspicion, wherein a feature of the region can raiseor lower suspicion. A taint vector can be configured to focus more onthe type rather than origin of malicious event or condition that occurs.The taint vector can include primary and secondary criteria, andaccumulates suspicious actions while also considering indicial of levelsof suspiciousness including extra data and extra identifiers relating tothe actions for further analysis. Accordingly, although the taint vectorcan consider the source of an event or condition in determiningsuspiciousness, actions, consequences, and usage can be more pertinentto identification of an attack or malicious condition. For example,known system calls are associated with reading data off web pages andthus tagged as suspicious for further analysis in which the source ofthe system calls can be identified (for example via operating systemsoftware that injects a label identifying the source).

The taint vector can be configured to set a hierarchy of suspicion basedon the source, type, or identify of an event. For example, a bufferoverrun can be considered worse than a null reference. The source of theevent can be considered to assign a level of suspicion such as whetherthe sensor from a known and trusted bank or an unknown bank or foreignhack site.

Information can reach the taint vector from multiple various sources.For example, some system calls are associated with accessing informationfrom web pages. These calls are tagged and the operating system injectsa label indicating that the data originated from a web browser at aparticular identified site. The protocol for receiving a taint noticefor tainting originating in a remote system outside the system whichcontrols the taint vector can be that the taint notice is placed bysoftware as some level, possibly software in the remote system. Thetaint notice is received from software from various sources such as byforwarding from the originating source, determined by a personattempting to write to a web browser, originating from suspiciousoperations or faults (such as buffer overflows), and, generally, from anindication that data has some level of questionability.

The taint vector can be implemented to include tolerances set based onquestionability of the source or event. Zero tolerance can be set forparticularly suspicious or harmful events and/or sources wherein asingle event can result in a maximum response. For a low threshold, theresponse for one taint can result in a trap, exception, or shutdown, andmay be used, for example, in nuclear power plant control.

A medium threshold can be a hybrid of low and high threshold and callfor a medium response and include aspects of decay. An illustrativesetting for medium threshold may allow two taints per hour and thus havedecay of one taint per half hour. In a typical condition such as onebuffer overflow per X amount of real time or CPU time or other interval,a monitor tracks events. Decay is implemented to account for rare andspurious events that are likely to occur by chance when monitoringcontinuously for vast time spans, and do not surpass threshold for anerror condition. Decay is thus is imposed upon accumulation sotriggering occurs when more events per unit time (other interval,instruction cycles, and the like) than accommodated by decay areindicative of an error condition. If events occur too often, thethreshold of rate of occurrences indicative of suspiciousness (taintrate) is too high and the threshold can be reset.

An example of high threshold can allow twelve taint counts per unit timesuch as for cheap video forwarded from a provider or signals fromubiquitous cell phones. Most events can be ignored in the absence ofsome indication of attack. Thresholds are set to balance a sufficientlevel of security with communications characterized by large amounts ofdata and frequent errors.

If taints exceed the threshold, then suspicion if sufficiently greatthat some action or response is taken. A suitable response can be trap,exception, notification, alarms, and the like.

In various system embodiments, taint vectors can be configured atselected locations and with selected granularity. A simple system canhave a single taint bit. A slightly more complex system can have asingle taint vector allocating multiple entries. Additional control andfunctionality can be attained by assigning a taint vector per register,for example to track computer processor register EAX (in 32-bit IntelArchitecture IA-32) while not tracking register EBX.

A taint vector can be configured to track memory taints, for exampletracking every byte in a computationally and resource expensivearrangement. In contrast, a less extensive implementation can assign asingle taint for all memory such as with 64 entries. A vector of 64entries may have one bad indicator operable as a running gauge ofoperations. The taint vector can indicate on/off status or a range.

Taints can be allocated by memory page. This might be challenging forsome existing processors, such as Intel processors, since no free bitsare available and page tables are read-only. To address this challenge,a system can include a memory taint hash table which, if read-only, canindicate a level of taint per memory block. A read-only memory preventslogging of taints in memory so that the table is located outside of theread-only memory. The amount of memory for the table can be reduced byusing a hash. Memory at the hash of an address can be used to compressthe address, for example 4 gigabytes (GB) can compress to a 64-kb table.A special instruction can be specified in which store memory at aspecified address receives a predetermined value.

Taints can be allocated by byte to attain the finest possiblegranularity. A special instruction can be specified in which memory at aspecified address has a taint field equal to a predetermined taint fieldvalue. Another example special instruction can be specified to create ataint hash vector in which memory receives a specified hash of theaddress where the hash is operable to compress the address, for example4-GB of memory can be compressed to a 64-kb table. Once the hash isperformed, security is no longer determinant or precise so that falsepositives can occur. The false positives can be addressed usingintrusion detection capabilities of the system. The taint hash vector iscostly in terms of resources, possibly 1-2 bits per byte maximum—asubstantial amount of overhead.

A taint vector can be configured to segregate memory by type, forexample distinguishing memory for storing program code from memory forstoring data. Different types of segments can be allocated forcorresponding different granularities of taint information.

Taints can be allocated by hardware process identifier (PID). Forexample, one vector can be allocated per hardware thread to addresscontext switching wherein a software thread's vector is stored.

In another option, taints can be allocated wherein a cross-thread taintis enabled, for example to address some system-wide taint.

In various embodiments, the operation of tainting can be allocated amonghardware devices and components and software. In a particularembodiment, hardware can track taints while software can inject initialtaint notifications, except when hardware can determine a priori that anevent or operation is bad. In example functionality, hardware cangenerate a trap to software according to predetermined “trap-if” rulesthat are most suitable selected so that rules are simple and easy todescribe, are activated in response to a specific condition, and easy toimplement. A trap can be activated based on selected thresholdconditions.

In various system embodiments, taint vectors can be configured withselected decay and using selected decay mechanisms. Decay can be appliedperiodically for example either on a consistent basis or with a varyingperiod based on a sensitivity meter. Characteristics of the sensitivitymeter such as rate of subtraction can be selected based on theenvironment of a system, for example whether a computer is running on ahome network, a business environment, a public network, and the like.

Decay methods can include subtraction of selected number N or shiftingthe taint vector in an interval of time, instruction count, or othersuitable metric (time periods, processor frequency or cycles, and thelike). The decay parameter and rate can be programmable. The rate and/orperiod can vary with the sensitivity meter, also possibly in aprogrammable manner, based on conditions such as type of network (home,public, work), activity (gaming, web browsing, office or scientificapplications), and other conditions, for example multiple taints from aknown particularly untrustworthy source. The rate and/or period can alsovary according to hardware environment or perspective, for examplewhether the hardware is constrained to a fixed rate or enabled for aprogrammable rate such as via a register loaded by software withpertinent information.

A special instruction can be created to facilitate setting of thesensitivity meter. The instruction can operate in conjunction with theoperating system to read a register indicating the level of protectionand can change the rate in response to operation of the sensitivitymeter.

A Taint Adjustment Vector (TAV) can be formed to adjust rate and perioddynamically. The TAV can comprise a timer register which canautomatically decrement a set of rates. In an example of TAV operation,the TAV including one or more taint adjustment vector parameters can beapplied to the Taint Vector (TV) upon expiration of the timer. Invarious implementations, the TAV can be applied to the TV by adding theTAV to TV, adding a delta, adding another selected value, shifting,shift-add, multiply, divide. Multiple timers can be used to enable decayfor one type of information to be different from decay for another typeof information. Taint Adjustment Vectors or timers can be universal overmultiple Taint Vectors or per Taint Vector.

A special instruction, for example a system-level “set taint vectorparameter” instruction, can be created to support the TAV. Theinstruction can act under operating system control in conjunction withmultiple timers, each of which controls a set of taint adjustmentparameter vectors (TAVs) which are used to adjust the current taintvector. The instruction can set the TAV and/or timer. The instructioncan write to a control register and allocate the control register incontrol register space as a TAV or timer.

Another technique for delay can be recursive addition of a Taint BiasVector (TBV) to the Taint Vector (TV), enabling the operating system tocreate complicated algorithms in the operating system time stampindependently of hardware operation and thus enabling flexibility inmodifying, selecting, and executing the algorithms. The algorithms cangenerally include primitive operations such as a shift, an add, and asubtract, although any suitable operation can be performed. TBV can belarger in number of bits than TV. Bias can constrain softwarefunctionality, for example increasing or decreasing the level ofsensitivity based on relatively complicated factors since the softwaremay not be completely trusted. Bias can also constrain operation bypreventing instant decay (bias may not be allowed to fully eliminatesecurity), although the operating system can be configured to authorizeor enable setting of instant decay.

In various system embodiments, taint vectors can be configured withselected taint elements to describe selected taint events.

Accidental/non-malicious overflows can be taint events. Taint handlingcan be constituted to handle legitimate overflows which can occursporadically and can be expected to occur. Overflows are examples ofknown problems. Special instructions can be created to address suchknown problems. Hints can be used in association with instructions, forexample by hint instructions which are dedicated to hint handling or byadding a hint bit field to an instruction. In the case of overflow, ahint can be used to notify that a particular instruction, for examplethe next instruction, may overflow.

Hint handling can be added to a taint vector, or to an “ignore problems”variety of taint vector. For example, a HINT instruction can beconstituted that, rather than the occurrence of a taint causingaccumulation of the taint vector, a count can be added to an IgnoreProblems Taint Vector (IPTV).

A predictive hint can also be used to allocate resources. For example, asoftware routine can use a hint a prediction of a significant amount offloating point usage. A HINT instruction can be included in the routine.In another version, at the beginning of a library function, code can beinserted to enable predictive preferential scheduling. The HINTinstruction can be part of the library, for example at the beginning, orassociated with the library. Code can be inserted in the library, suchas at the beginning of a library function requesting particularresources, for example for preferential scheduling. In one example form,a call to a system call can request the operating system to allocatemore resources. In another example form, a hint instruction can be sentto hardware to implement the hint and the hardware responds by using thehint in hardware scheduling, such as push, pop, pull, stack, or thelike. The hint instruction typically has no direct effect on programexecution. The program will run correctly except for changes inperformance and battery life.

Predictive hints can also be implemented other than with a hintinstruction. Rather than an instruction, the hint may be part of thedata structure. For example, X number of bits can relate to expectedcapabilities to which a process can be entitled such as a vector or astructure. Software can determine information for a performancedescriptor, then fills in the data so that metadata of a descriptordetermines importance of the performance descriptor.

Accordingly, predictive hints can be implemented in hardware, software,the instruction set architecture, or a combination of configurations.Hardware is typically more constrained than a software implementation. Asoftware library enables the hint to be passed in a linked list of hashtrees for passage into hardware, for example as a 128-bit or 256-bitregister. Such an implementation can be implemented in an applicationprogramming interface (API) but sufficiently simple to be part ofhardware. Thus, the API can be designed, then simplified sufficiently toput into hardware.

A taint vector can be used to simultaneously manage, monitor, analyze,and respond to taints associated with various resources independentlyfrom one another. The taint vector can be specific to particular sourcesand resources including networks, systems, processors, memory, hardware,software systems, virtual entities, and the like, including variousaspects of operation. The taint vectors can operate on a resource pooland enable detection and resolution of various types of taints.Accordingly, the taint vectors can be used to manage security risks andfaux paus of resources.

In information handling systems such as computers, operating systems,communication systems, networks, and the like, a trap, which can also betermed an exception or fault, can be invoked as a type of synchronousinterrupt caused by predefined exceptional conditions such as abreakpoint, null pointer reference, division by zero, invalid memoryaddress, and the like. A trap can result in a context switch such as aswitch to kernel mode, wherein the operating system performs apredetermined action before returning control to an originating process.A trap in a system process is generally more serious than a trap in auser process, and in some systems is fatal. In some system definitions,the term trap refers specifically to an interrupt intended to initiate acontext switch to a monitor program or debugger. A variety of other trapoperations are possible.

A trap can be thrown based at least partly on a current value of anentry of a taint vector. As taint vector entries are increased, a trapcan be thrown based on a current value of a taint vector entry or one ormore thresholds. Thresholds can vary by affiliate, current systemcharacteristics or activities, and the like. Conditions can involve oneor more comparisons between taint vector entries and thresholds.Thresholds can be entry-specific, apply to similar affiliates, beuniversal, be for a sum of taint vector entries, and the like.Thresholds can be set or changed to reflect different tolerance levels.A variety of target functions, weights, masks, can be implemented.Referring to FIGS. 1A, 1B, 1C, 1D, and 1E respectively, first, second,third, fourth, and fifth schematic block diagrams depict embodiments ofan electronic device 100, and can respond to predetermined taintconditions by trapping. FIG. 1F is a graphical data description showingan aspect of operation of the electronic device 100. FIGS. 1G and 1H aredata structure diagrams illustrating example embodiments of taint vector104. An illustrative embodiment of an electronic device 100 can comprisean input interface 108 and a hardware component 110 coupled to the inputinterface 108. The input interface 108 can be operable to receive aplurality of taint indicators 107 corresponding to at least one of aplurality of taints 105 indicative of potential security risk which areinjected from at least one of a plurality of resources 102. The hardwarecomponent 110 can be operable to track the plurality of taints 105.

The electronic device 100 can be configured wherein the input interface108 is operable to receive at least one taint indicator 107 from atagged system call 122 associated with accessing information from a webpage 123. An operating system 124 can inject a label 125 originatingfrom a browser 126 at an identified site. In various embodiments, theelectronic device 100 can be operable to respond to security risk upondetermination of the at least one security risk event by a responseselected from various responses such as ignoring a security risk event,logging the at least one security risk event, displaying a notification,displaying a warning message, generating an alarm, and the like. Otherresponses can extend beyond passing of information to dynamic managementand control of system operations such as preventing a memory and/orregister write, modifying operating frequency, modifying operatingvoltage, modifying an operating parameter, performing a system call, andthe like. Even more drastic responses can terminate a particularprocess, and end operations of some or all resources, for example bycalling a trap and/or exception, terminating operation of selectedresources, activating a system shutdown, and the like.

In various embodiments, tainting can be distributed among hardwaredevices and components and software. In a particular embodiment,hardware can track taints while software can inject initial taintnotifications, except when hardware can determine a priori that an eventor operation is bad. Accordingly, the electronic device 100 can beconstructed such that the hardware component 110 is operable to injectat least one taint 105 of the plurality of taints 105 when the at leastone taint 105 is known a priori to indicate an event 116 and/orcondition 120 is suspicious.

The systems and techniques disclosed herein are operable in the contextof physical hardware and software-oriented configurations. The systemsand techniques are further operable for embodiment as virtual computersand devices presented or emulated within a virtualization system. Thus,the electronic device 100 can be used in physical hardware systems,virtualized systems, and combination systems with both physical andvirtual aspects, with functionality distributed across devices orsystems. Thus, taint information can be received from a source remotefrom a targeted system, such as from an interface, a network, a gateway,remote computer, or the like.

Taint information can be received from some source and can be destinedfor some target storage location and downstream usage. Information ordata can be considered tainted, potentially tainted, suspect, or knownuntainted based on multiple criteria. Tainted information or events aredefined according to a particular implementation and security policy ina range from “of interest,” potentially untrusted, and suspect tountrusted, potentially dangerous, and malicious. Information can beconsidered tainted based on entity including source, target, andinterface; and also based on characteristics or conditions ofinformation receipt such as conveying protocol or transaction; or basedon a combination of considerations.

In various embodiments, the electronic device 100 can handle taints ofvarious types. For example, the electronic device 100 can be configuredsuch that one or more of the plurality of taints can be selected fromamong null pointer references, attempts to access a secured part of aprocessor, attempts to access a secured resource, buffer overruns,events originating in a region that raises suspicion, faults, integeroverflow, multiple taint indicators that exceed at least onepredetermined threshold, a taint indicated by power law analysis, ataint indicated by a race function, attempts to access a key, and manyothers.

Another aspect of electronic device operation is specification and usageof a taint vector 104 to enable monitoring and tracking of a largenumber of resources and conditions or a wide variety of types withoutburdening the system and operations with a significant amount ofhardware and complexity. For example, referring to FIG. 1B, theelectronic device 100 can further comprise at least one taint vector 104and monitoring logic 128. A taint vector 104 can be operable to track atleast one taint 105 of the plurality of taints 105 indicative ofpotential security risk originating from at least one of the pluralityof resources 102. The monitoring logic 128 can be operable to monitorthe at least one taint vector 104 and detect a predetermined taintcondition 106 wherein a predetermined condition of data is indicated.

In some embodiments, the monitoring logic 128 can be operable toincrement the at least one taint vector 104 upon detection of apredetermined taint condition 106 wherein a predetermined condition ofdata is indicated.

In various embodiments, the electronic device 100 can be constituted toimplement a wide range of accumulation functions. For example, theelectronic device 100 can comprise monitoring logic 128 operable toaccumulate the plurality of taint indicators independently using one ormore of a plurality of accumulation functions 140. The accumulationfunctions 140 can be selected from among comparing ones of theaccumulated plurality of taint indicators to at least one predeterminedthreshold, performing power law analysis, and/or performing a racefunction. The electronic device 100 can be formed such one or more ofthe taint vectors can be operable as an accumulator for counting thenumber of tainted instructions. Other suitable accumulation functionscan operate by counting various occurrences or aspects of operation suchas counting a number of taints, counting a number of taints taintspermemory unit, counting a number of instructions tainted, counting anumber of tainted instructions, counting a number of instructionswritten as a result of a taint, counting a number of data loads andstores, counting a number of memory accesses, counting a number ofcalls, counting a number of returns, and counting a number of branches.Still other counting aspects of accumulation functions can includecounting the number of integer overflows, counting the number of networkinput/output events, counting the number of null pointer references,counting the number of buffer overruns/overflows, counting the number ofrepeated attempts to access a key, and the like. Suitable accumulationfunctions can be used to monitor any aspect of operation.

In some embodiments, one or more of a plurality of accumulationfunctions 140 can be implemented via a taint vector 104. Thus, theelectronic device 100 can be configured wherein ones of the at least onetaint vector 104 can be operable as an accumulator of a plurality oftaint indicators 107 indicative of potential security risk from aplurality of distinct sources 115 at distinct times.

In various embodiments and/or conditions, the electronic device 100 canbe configured to address intrusion for a variety of resources 102 at avariety of levels of granularity. For example, the electronic device 100can be operable to configure bit fields of the taint vector at aselected granularity including a taint bit per entry, a taint bit perregister, a taint bit per multiple entries, a taint vector per entry, ataint vector per register, and a taint vector allocating multipleentries. Furthermore, in various embodiments and/or conditions, theelectronic device 100 can comprise monitoring logic 128 which isoperable to allocate taints at a selected granularity. The variouslevels of granularity can include allocating taints by memory page,allocating taints by byte, allocating taints by word, allocating taintsby memory block, and allocating taints by hardware process identifier(PID). Other levels of granularity can include allocating taints toenable a cross-thread taint, allocating taints among hardware devices,allocating taints by component, allocating taints by software component,and the like.

In some embodiments, for example as shown in FIG. 1H, the electronicdevice 100 can be configured wherein the monitoring logic 128 isoperable to acquire and monitor a history of the ones of the at leastone taint vector 104 in a feedback loop 142 that correlates taints 105with responses to the taints 105.

Several target functions, weights, masks, can be implemented fortracking and responding to taints. For example, embodiments of theelectronic device 100 can further comprise monitoring logic 128 operableto apply at least one function 144 to the at least one entry 103 of theat least one taint vector 104.

In various embodiments, the electronic device 100 can be configuredwherein the at least one function 144 can be selected from variousfunctions such as weights, masks, sums, combinations, arithmeticfunctions, logical operations, transforms, and the like.

Taints can be generated on the basis of questionability of the data andof other aspects of operation and condition such as prior negativeexperience or lack of familiarity with a data source or entity. Forexample, the electronic device 100 can be configured to includemonitoring logic 130 which is operable to determine whether informationfrom a particular source or entity is trusted based on assessment ofsecurity risk. Thus, in a further aspect of operation, shown in FIG. 1B,embodiments of the electronic device 100 can further comprise monitoringlogic 128 operable to acquire a history of the ones of the at least onetaint vector 104.

In various embodiments, the monitoring logic 128 can be constituted toperform various tracking and monitoring operations to enable enhanceddetection of intrusion. For example, in some embodiments the electronicdevice 100 can be configured wherein the monitoring logic 128 is furtheroperable to track taint indicators 106 characterized by a range oftaintedness from potentially suspicious to definite taints 105.

The monitoring logic 128 can be constructed to perform variouscomparisons to indicate error or intrusion. For example, the electronicdevice 100 can be configured wherein the monitoring logic 128 is furtheroperable to monitor comparisons selected from a group includingdetermining whether any elements are greater than a predeterminedthreshold, determining whether all elements are greater than apredetermined threshold, determining whether the sum of some elements isgreater than a predetermined threshold, determining whether the sum ofall elements is greater than a predetermined threshold, and the like.

The electronic device 100 can be configured to discern actual securityrisks from innocent and/or coincidental events. For example, in someembodiments the monitoring logic 128 can be operable to monitor theplurality of affiliates 113, system characteristics 114, sources 115,events 116, activities 118, and/or conditions 120 to detect and discernone or more potentially innocent and/or coincidental events such as nullpointer references, attempts to secure part of a processor, innocentand/or coincidental events arising from a region that raises suspicion,and the like.

In various embodiments, the electronic device 100 can be operable tospecify one or more of a plurality of decay options selected fromapplying decay after a predetermined number of operations to avoidtriggering on outlying events, setting decay to account for rare andspurious events with a probability of occurrence by chance during longterm monitoring, incrementing/decrementing using a single vector, and/orsubtracting a predetermined number. Other suitable decay options caninclude shifting a taint vector 104 in an interval of time, shifting ataint vector 104 at a predetermined instruction count, shifting a taintvector 104 at a predetermined processor cycle count, copying a taintvector 104 periodically to memory to maintain an old version whileincrementing/decrementing to enable restoration following an invalid orerror condition, and imposing decay that balances accumulation. Furtherexamples of suitable decay options can include applying decayperiodically, applying decay with a varying period that varies based ona sensitivity meter, applying decay with a varying period that variesbased on environment, applying decay with a varying period that variesbased on activity type, applying decay according to a programmableparameter at a programmable rate, and the like.

In some embodiments, as depicted in FIG. 1C, the electronic device 100can include response logic 130 to respond to a taint conditiondetermined during taint vector tracking. Hence, the electronic device100 can further comprise at least one taint vector 104 and responselogic 130. The at least one taint vector 104 can be operable to list atleast one taint 105 of the plurality of taints 105 indicative ofpotential security risk originating from at least one of the pluralityof resources 102. The response logic 130 can be operable to respond to apredetermined taint condition 106.

For example, the monitoring logic 128 can monitor network communicationtraffic and response logic 130 can respond to tainted traffic on thenetwork. Accordingly, the electronic device 100 can be configured tofurther comprise monitoring logic 128 operable to monitor taints 105 innetwork 136 input/output operations, and response logic 130 which can beoperable to trap to a software process 132 based at least partly ondetermination of a network 136 input/output condition of an attempt ofmalware 137 to communicate to a malware operator 138.

In some embodiments and/or conditions, the electronic device 100 canfurther comprise monitoring logic 128 operable to monitor taints 105using a hardware device 109, and response logic 130 operable to insertinitial taint notifications using a software process 132.

In various embodiments, applications, and/or conditions, the electronicdevice 100 can respond to security risk upon detection of a securityrisk event using one or more responses selected from responses thatrange from relatively minor informational actions to actions which canmoderately or substantially change system operations, or even terminatesome or all system operations. Accordingly, some embodiments of theelectronic device 100 can further comprise response logic 130 operableto respond to at least one security risk event with at least one minorresponse selected from among ignoring a security risk event, logging thea security risk event, displaying a notification, displaying a warningmessage, generating an alarm, and the like. When limited intervention iswarranted, the response logic 130 can be operable to respond to at leastone security risk event with at least one limited intervention responseselected from among preventing a memory and/or register write, modifyingoperating frequency, modifying operating voltage, modifying an operatingparameter, performing a system call, and the like. For security riskdetermined to be more serious, the response logic 130 can be operable torespond to at least one security risk event with at least one systemintervention response selected from among calling a trap and/orexception, terminating operation of selected resources, activating asystem shutdown, and the like.

Referring to FIG. 1D, embodiments of the electronic device 100 can beconfigured wherein the plurality of taints 105 can be injected byselected ones of the plurality of resources 102 including physicaland/or logical instances of processors 145, central processing units(CPUs) 146, graphics hardware 147, network controllers 148, memory 149,memory management 150, hardware 151, microarchitecture 152, sound cards153, video cards 154, network interfaces 155, instruction setarchitecture (ISA) 156, library calls 157, library functions 158,software objects 159, compilers 160, operating systems 124, and thelike.

The electronic device 100 can be operable as at least part of anetworked system including multiple computing devices such as electronicdevice 100 which interfaces with remote and potentially untrustedcomputers and may be the source of security risk events such as attacks.Security risk events or attacks can arise from other sources includingcomputing devices and systems, storage and devices inside a firewall orlocal to a targeted machine. In general, computers and networks canrepresent a variety of local or globally distributed systems andnetworks that can supply information via a plethora of communicationchannels and protocols such as the Internet.

Security risk events and attacks can originate remote from a local andpotentially trusted network, and can similarly originate from localusers, systems, devices, and storage. Accordingly, the electronic device100 can be constituted to address security risk events that arise from alocal device such as keyboard, network interface, communication devices,local storage including memory and long-term storage devices, and othercomputers and systems.

Referring to FIG. 1E, taint information can be received from a sourcethat is remote from a targeted system, such as from an interface, anetwork, a gateway, remote computer, a cloud, and others. Thus, theelectronic device 100 can be configured wherein ones of the plurality oftaints 105 are injected by a resource 102 of the plurality of resources102 that is remote from the electronic device 100. The at least onetaint indicator 107 corresponding to the injected ones of the pluralityof taints 105 can be communicated to the electronic device 100.

In a more specific embodiment, the electronic device 100 can beconfigured such that one or more of the plurality of taints 105 areinjected by remote software 162 that is remote from the electronicdevice 100. The at least one taint indicator 107 corresponding to theinjected ones of the plurality of taints 105 is communicated to theelectronic device 100.

In some embodiments and/or in particular conditions, taints from localresources can be tracked and handled. For example, the electronic device100 can be configured wherein ones of the plurality of taints 105 areinjected by a resource 102 of the plurality of resources 102 that islocally coupled to the electronic device 100. At least one taintindicator 107 corresponding to the injected ones of the plurality oftaints 105 can be directly accessed by the electronic device 100.

In more specific embodiments and/or conditions, the electronic device100 can be configured such that one or more of the plurality of taints105 are injected by local software 164 that is local to the electronicdevice 100. At least one taint indicator 107 corresponding to theinjected ones of the plurality of taints 105 can be directly accessed bythe electronic device 100.

Referring again to FIG. 1E, a electronic device 100 can be operable asat least part of a federated system which can be implemented in aninfrastructure such as an architecture including servers and clients.For example, gaming code servers and gaming console clients can interactby running program code that executes in part on machines controlled bythe server and in part on machines controlled by the client. Intrusiondetection via accumulation of taints can enable the interaction to bemutually trusted by both sides. In an illustrative embodiment, theelectronic device 100 can be operable as at least part of a federatedsystem comprising a least a first source 115(1) and a second source115(2). Accordingly, the electronic device 100 can be configured whereinones of the at least one taint vector 104 comprise an entry 103 that isallocated to selected ones of the plurality of resources 102. The taints105 of the selected ones of the plurality of resources 102 can befederated to the entry 103.

Referring to FIG. 1F in combination with FIGS. 1B and 1C, a graphicaldata description shows an example operation that can be executed by theelectronic device 100 to facilitate intrusion detection using taintaccumulation. In an illustrative embodiment, the monitoring logic 128can be operable to monitor taints 105 and create a trust profile 134based on the monitoring; and response logic 130 operable to trap to asoftware process 132 based at least partly on determination of asuspicious condition. For example, the monitoring logic 128 can form thetrust profile 134 using accumulated taint indicators, dynamically raiseand lower trust level of the trust profile 134 based on the accumulatedtaint indicators, and respond to security risk in response to the trustlevel.

As shown in FIG. 1G, various aspects of taint vector 104 locationsand/or granularity can facilitate intrusion detection using a taintmechanism. In various embodiments, the electronic device 100 can beconfigured such that the plurality of taints 105 comprise one or more ofa plurality of distinct classes 112 comprising a plurality of distinctaffiliates 113, system characteristics 114, sources 115, events 116,activities 118, and/or conditions 120.

In some embodiments, the electronic device 100 can be configured whereinones of the at least one taint vector 104 comprise a composite taintvector 166 that correlates a taint source 167 and a taint activity type168.

A taint indicator can be generated in association with operation of atranslation lookaside buffer (TLB) in a processor. A translationlookaside buffer (TLB) is a processor cache which can be used by memorymanagement hardware to improve virtual address translation speed.Processors use a TLB to map virtual and physical address spaces. TLB areused widely in hardware which uses virtual memory.

The TLB can be implemented as content-addressable memory (CAM), using aCAM search key which is the virtual address to produce a search resultwhich is a physical address. If the TLB holds the requestedaddress—called a TLB hit, the CAM search quickly yields a match and theretrieved physical address can be used to access memory. If the TLB doesnot hold the requested address—a TLB miss, the translation proceeds bylooking up the page table in a process called a page walk. The page walkis computationally expensive process, involving reading contents ofmultiple memory locations and using the contents to compute the physicaladdress. After the page walk determines the physical address, thevirtual address to physical address mapping is entered into the TLB.

A stream monitoring instruction can be implemented to improve efficiencyand performance of the TLB by supporting a software predictor. Theinstruction can be used to monitor misaligned or split access. A memoryaccess is aligned when the data item accessed is n-bytes long and thedata item address is n-byte aligned. Otherwise, the memory access ismisaligned. Monitoring for misaligned access can be performed byhardware, resulting in a trap, or somewhat less efficiently by software.In practice, monitoring for misaligned access has a high false positiverate, for example approaching 90%. A predictor can be configured, forexample by micro-architecture adjustment or taint accumulation, toindicate whether the misaligned access hits are accurate.

The processor can be configured to change voltage, frequency, and/orpower based on the number of cache misses. For example, logic canaccumulate taint indicators to detect an abundance of cache misses orother performance problems, the voltage can be varied such as increasedto cure the problem. The logic can dynamically adjust operatingparameters according to the amount of traffic. Frequency and voltage canbe adjusted, for example whenever a change in frequency occurs, thevoltage can be modified accordingly.

Logic in a memory interface can detect when memory is full to somethreshold level, for example 70%, for example by accumulating taintindicators. If memory is full to the threshold level, a predeterminedtaint indicator condition is found, and a high level of access isoccurring, memory speed can decrease. In response, the frequency andvoltage of operation can be dynamically increased to maintain a desiredmemory speed.

In various embodiments, logic for performing dynamic adjustment can bepositioned in memory, in a logic interface, in a processor. A hardwareconfiguration can optimize by active adjustment, redirection, orpossibly a combination of adjustment and redirection. For example, acomputation-intensive process with many instructions to be executedrapidly can be addressed by running the processor at a higher rate byincreasing operating frequency and voltage, and/or some of the burdencan be shifted to components other than the processor to maintainprocessor execution at a lower frequency.

Taint accumulation can also be used to allocate system resources.Various aspects of resource allocation include hardware threading,computational limits, pooled resources, entitlements, and others.Resource allocation can be handled via various architectural aspects ofa system including microarchitecture, instruction set architecture(ISA), operating system, library calls, and taint accumulation. Softwarecan associate capabilities with particular library functions or softwareobjects. This software can be in the form of compiler, operating system,or others. The operating system can, for example, create a profile forany process running floating point operations and give that entitlement.Resources allocated include processors, central processing units (CPUs),graphics hardware, network controllers, memory, memory management, otherhardware, and the like. Resources further include power, cycles, and thelike.

Hardware threading.

Several aspects of hardware threading are currently implemented inprocessors such as CPUs. Simultaneous threading (SMT), hyperthreading,or simultaneous hyperthreading relate to hardware execution of two orfour threads selected for running at any time, managed according to manyfine-grained scheduling decisions. In a cycle, two threads are selectedat instruction fetch, typically at the front of the pipeline andhardware determines which of the two thread's instructions to fetch. Aninstruction for each of the threads pass to an out-of-order machinewithin which the instructions are running concurrently. For example, anarithmetic logic unit (ALU) instruction from thread 1 and a memoryinstruction from thread 2 can run simultaneously.

Another type of hardware threading is interleaved multithreading (IMT)which removes all data dependency stalls from the execution pipeline.One thread is relatively independent from other threads so theprobability of one instruction in one pipeline stage needing an outputfrom an older instruction in the pipeline is low. IMT is conceptuallysimilar to pre-emptive multi-tasking used in operating systems.

In contrast to CPU multithreading which handle relatively few threads(typically two or four threads), graphics processing units (GPUs) arestream processors for computer graphics hardware and manage hundreds orthousands of threads, thus using much more sophisticated scheduling.When blocking occurs, for example on a cache miss such as from a memoryreference, a very large number of threads are blocked. Threads arechosen for execution on massively parallel thread arrays. In a typicalarrangement, a processor has approximately 64,000 threads of which onlyabout a thousand execute at one time. Underlying operations duringexecution include scheduling, addressing cache misses, and the like.Rather than scheduling from a memory pool, GPUs schedule instructionsfor execution from a very large pool of threads, waiting for memory tobecome available to run the next thread.

A CPU can be configured for a CPU thread hierarchy which includes acurrently running list and a pool of non-running threads enabled toreceive information pertinent to computational limits from devices orcomponents such as special-purpose hardware. In an illustrativeembodiment, the information pertinent to computational limits can bemonitored via taint indication and taint accumulation, and resourcesallocated accordingly.

Computational limits can be imposed via generation of taint indicatorsand taint accumulation. A limit on computation can be imposed accordingto setting of priority level which is, in turn, based on availableresources. One example resource that can be monitored to set limits oncomputation is the battery. Limits on computation can be imposed basedon battery consumption, battery life remaining. Computational limits canbe addressed via a framework of setting capabilities, for examplespecifying a capability to execute on selected processing resources. Inan example implementation, the capability can be set up in metadata.

Taint accumulation is suitable for managing computational limits sinceaddressing computational limits can be fairly complex, involving notonly information from monitored resources but also user input. Forexample, a determination by hardware of low battery level and associatedlimited battery life can be overridden by a user who may request asoftware application to run in anticipation of being able to soonrecharge the battery at a line power source.

Performance capabilities can be used in combination with taintaccumulation to manage resources. A performance capabilities frameworkcan be defined to address handling of a pool of available resources. Athread pool pattern can be configured wherein a number of threads arecreated to perform a number of tasks which are typically organized in aqueue. Usually, the number of tasks is greater than the number ofthreads. A thread upon completing an associated task will request thenext task from the queue until all tasks have completed. The thread canthen terminate or become inactive until new tasks are available. Thenumber of threads can be tuned to improve performance, and can bedynamically updated based on the number of waiting tasks. Increasing thesize of the thread pool can result in higher resource usage.

A hardware scheduler can respond to any countable or measurableoperating condition or parameter, for example electrons, constraints,frequency, cycles, power, voltage, and the like, to control the threadpool and pool of resources. The countable or measurable operatingconditions and/or parameters can be monitored over time using taintaccumulation. Two highly useful conditions or parameters for monitoringare power and cycles, which are the basis for other measurablephenomena. Monitoring of operating conditions can be performed inhardware or via software call.

Furthermore, software can associate capabilities with particular objectssuch as libraries.

Taints for main memory may be located in different places, organizeddifferently among different memory locations or types, and/or associatedwith different amounts of memory. In an example configuration, a singletaint vector can be allocated for all main memory, which can havemultiple entries that are associated with different memory ranges.Taints can be organized by or applied to memory pages. Level of taintmay be indicated per memory block. A separate taint table can be used ifa general page table is read-only, and a size of a separate taint tablemay be reduced via hashing. Taints can be applied on a per-byte basis,but then likely only 1-2 bits and significant overhead. Accordingly, asshown in FIG. 1D, taints can be associated with main memory tofacilitate intrusion detection in a taint mechanism. Thus, variousaspects of taint vector location and/or granularity can be formed inmemory.

In an example software embodiment, software can monitor the system overhistory, or can be preprogrammed, and fills in some sets in entitlementvector fields. Software can determine values for the fields and fill inthe bits of data, possibly associated as a lookup table, an associatedhash table, an extra field to call for a library, and the like. For alibrary call, an entitlement vector EV is returned. The entitlementvector can be received from various sources, for example from externalto calling software. For example, the entitlement vector EV may beinstalled into hardware as a side effect of the library call.

A factor in determining whether the entitlement vector is handled insoftware or hardware is the size of the vector.

In an example hardware implementation, a suitable entitlement vectorsize is 256 bits, although any suitable size is possible. For example, avector of 64K bits is generally considered too large for hardwareimplementation.

In some embodiments, an entitlement vector can be associated with eachlibrary. The entitlement vector can be used, for example, to eliminatefloating point if desired, reduce the number of floating pointoperations if such operations are rarely used, reduce the scale asappropriate when full accumulator width is unnecessary, increase supportfor the ALU.

The entitlement vector can be implemented as a call with a memoryaddress made in association with a call to a library which, for example,can return a pointer or address location to the entitlement vector.

Another field of the entitlement vector can be a chooser/threadselector. The entitlement vector can be used by the chooser/scheduler,which includes logic that performs operations based on a singleentitlement vector or possibly relative entitlement vectors. EachInstruction Pointer (IP) or thread can have an associated entitlementvector. For example instruction pointers, for IP1, IP2, IP3, IP4, thenfour entitlement vectors can be allocated. Chooser/scheduler logicconsiders the entitlement vector when scheduling the next thread forcomputation. The logic informs the chooser/scheduler about how to makethe selection. The logic can perform selected functions to make thechoice and for scheduling, for example by elevating or decreasingpriority of a thread.

An example function using an entitlement vector (EV) can compute the sumof weight times EV_(i) compared to the usage vector of Thread_(i), asimple target function for evaluating when to schedule threads from thehighest priority to the lowest priority. Thus, for a thread with highpriority and large requirement for resources, the thread can be elevatedin the scheduling list and resources are likely to be allocated. Incontrast, a thread that is a glutton for resources and has low priorityis likely to be deferred by the scheduler, moving back or to the end ofthe list of scheduled threads. A high priority thread that consumes onlylimited resources is likely to be moved up in the schedule list,possibly to the front of the list.

In some embodiments, the entitlement vector supplied by a HINTinstruction can be modified by a capability process. Illustratively, theentitlement vector can set entitlement to use X resources which can belimited by the operating system for example by reduced weighting orsetting of maximum allowed resources. The entitlement vector can also belimited according to usage, wherein a thread using an inordinately largeamount of resources can be limited when the high usage is detected orpredicted.

The entitlement vector function F_(i)(w_(i), EV_(i), v_(i)) of weight(w_(i)), entitlement vector (EV_(i)), and resource volume (v_(i)) can beeither linear or non-linear.

The entitlement vector enables association of scheduling with functions.The entitlement vector further enables association of priority withfunctions.

One of the challenges in allocating resources is the potential forhighly unpredictable changes in resource demand. For example, minorchanges in workload can result in substantial variation in performance.Another challenge is unpredictable behavior in response to contextswitches from one process to another. One technique for dealing withthese challenges is making a library call as a technique for determiningwhether a context switch occurred or, if not expecting to make a librarycall, perform an action that randomizes priority. If degradation resultsfrom making the library call, then performance can be monitored todetermine whether performance is reduced. If so, priority of the threadscan be randomized. Example techniques for randomization can include aBoltzmann search, simulated annealing, hop-around, other lateralcomputing techniques, and the like. A Boltzmann search can be performedby a Boltzmann machine, a stochastic recurrent neural network that iscapable of learning internal representations and solving combinatoricproblems. Simulated annealing is a computer technique used for answeringdifficult and complex problems based on simulation of how pure crystalsform from a heated gaseous state. Instead of minimizing the energy of ablock of metal or maximizing strength, the program can minimize ormaximize an objective relevant to the problem at hand, specificallyrandomization to attain stable performance. In a hop-around technique,priority or other parameters can be bounced around to determine a localmaximum but not global optimum. Search optimizations can be used todetermine whether truly at a maximum value. The new results can becompared with an old optimum.

In some embodiments, a supervisor circuit, for example for thermaland/or overvoltage protection, can modify the entitlement vector.

The entitlement vector, for example in combination with a usage vectorand/or taint accumulation monitoring, can be used for monitoring powercontrol. In various embodiments, power control monitoring can beperformed remotely or locally, possibly by the operating system.

In an example embodiment, a user can supply an entitlement vector usinginstructions, for example by specification of the beginning and end of afunction. The entitlement vector can be used in association with aperformance monitoring unit which monitors and determines otherentitlement vectors. In various embodiments, the entitlement vectors canbe maintained separately or combined into a single effective entitlementvector.

Context switches can be specified as taint indications for usage intaint accumulation. Context switches can be defined as switches from oneprocess to another. In contrast, a thread can typically be consideredlimited to a single context. Standard threads and mock threads shareresources including context and can have multiple processes, multiplethreads within the same privilege level technically. However, athreading library and threading operating system can be created whereinthreads are not limited to the same context. Threads can comprise simplya stack and an instruction pointer, and can run in the same addressspace, for example threads can run as different users in the sameaddress space. In a case of multiple users accessing the same database,if the database is a shared-memory database, software or an interpretercan be responsible for ensuring that unauthorized user(s) cannot accesscertain data. In the case of users assigned different privilege levelsor different threads in the same virtual memory address space assigneddifferent privilege levels, different registers are assigned toparticular users and/or threads, and thus switches between users and/orthreads are context switches.

Privileges can be associated with a page, a page table, an actualphysical memory address, a virtual memory address, and the like.

Capabilities and entitlement can be used in combination with taintaccumulation for managing resources. In some embodiments, thecapabilities vector and the entitlement vector can be merged. In someaspects of operation, entitlement can be considered to be a capability.With entitlements specified, the associated performance capabilities andmanagement of associated capabilities prevents unauthorized access todata and/or resources, and prevents system takeover, unless specificallyallowed or enabled by a system call, improving security and enablingdenial of service to attacks.

Merged capabilities and entitlement can be used to preventmicroarchitectural denial of service. Denial of service is typicallyconsidered to arise from a hacker on a network blocking access by usingup all or a substantial part of network bandwidth. For example, whenoperating on a virtual machine in a cloud computing platform (such asAmazon Elastic Compute Cloud (EC2)) a job can be run that thrashes thecache, resulting in an architectural denial of service in response.Preventative remedies can include checking for performance counters andpreventing such unauthorized accesses. Microarchitectural remedies canalso be used such as implementing microarchitectural covert channels inwhich, for various types of code, secret keys running on the samevirtual machine can be detected. Similarly, microarchitectural covertchannels can be used to monitor timing of code to detect intrusion andto detect whether a bit is set in a particular bit position which mayindicate intrusion. Microarchitectural techniques can thus includetiming channels and covert channels for use whenever a shared resourceis to be modulated. Covert channels can be applied, for example, inmodulating a disk arm, detecting seeks on a file system.

In various embodiments, operations implementing and using theentitlement vector can be executed by software in a processor, bymicrocode, in logic, in hardware, or the like.

An infrastructure configured to support multiple processors in a systemcan have a shared memory and message passing between threads, processes,processors, and the like. Operating systems (OS) can include variousmechanisms to enable message passing, for example pipelines, daemonsthat use sockets, loopback, and the like. Any suitable number ofprocessors can be supported in the system, from relatively small systemswith few processors to large scale systems with hundreds of thousands ormillions of processors. In a typical large scale system, the multitudesof processors communicate via fat trees which support the large amountof bandwidth demanded by the large scale system. The amount of bandwidthin different positions in the tree is variable, depending on traffic. Invarious other configurations, the many processors can communicate viameshes or buses, via Gigabit Ethernet, via CDMA-CE (Code DivisionMultiple Access-series CE), and the like. In large interconnects, thenumber of processors determines what functionality is attainable. Forexample, for more than about 1000 processors, memory can no longer beshared. At around 100 processors, memory space can be shared butcache-coherence is typically not possible and memory is thusnon-cache-coherent shared memory. Cache-coherence is generallyconsidered to cause problems for more than about sixteen processors sothat fewer processors at a first level can have cache-coherent sharedmemory.

For a supercomputer or other system with the large number of processors,for example more than about 1000, for which memory is non-shared,Message Passing Interface (MPI) can be used for communication. MPI usesmultiple threads but does not use shared memory. The MPI multiplethreads are all part of local shared memory, but no global shared memoryexists. The amount of local shared memory is limited, resulting in acommunications bottleneck. Supercomputer memories use Message PassingInterface (MPI) which, to a first order, includes a limited number ofinstructions such as send some location, buffer, end buffer, and receivesome entity, buffer, end buffer, and the like. MPI is an applicationprogramming interface (API) and is thus a library call. The receivedentity can be, for example, a channel connecting the sender and thereceiver, although channels are rarely used in MPI since channels do notscale beyond about a thousand processors. Accordingly, MPI can usecommands with masks which identify which processors are to receive amessage. A difficulty with MPI is that different code must be written,and a different core engine and interface, for small-scale andlarge-scale parallelism. Thus, send-and-receive communication such as isused by MPI is suitable if memory is shared.

What is desired is a technique for expanding send-and-receivecommunication more broadly. In accordance with system and methodembodiments, a communications application programming interface (API)can be created that enables communication between different types ofthreads and hides that the threads are sharing memory. Thecommunications API can enhance functionality of a Transmission ControlProtocol (TCP) socket. The TCP socket, also termed an Internet socketfor network socket, is an endpoint of a bidirectional inter-processcommunication flow across and Internet Protocol (IP)-based computernetwork such as the Internet. In some embodiments, the communicationsAPI can also incorporate functionality of MPI into that of a TCP socket.In a distributed system, a processor can communicate with a NetworkInterface Controller (NIC) and a send instruction puts data on a queueto send to the NIC and pass through the routing network to a specifieddestination. The communications API can perform communications viaTCP-IP, in some configurations optimizing aspects of TCP-IP such as byordering packets, and also via other protocols. The communications APIcan include send-and-receive functionality, and include one or morechannels, which is operable with TCP-IP. Some of the channels can beshared memory in the form of a buffer with a counter. Some channels canconnect to the NIC, some channels to TCP-IP, and some channels can haveother functionality. In some embodiments, the communications API cansupport different types of channels. One example of a channel type issimply registers. Another type of channel can run two hardware threadswith a pipeline coupled between the two threads.

The communications API can be adapted to handle the possibility ofoverflow. For example, for a channel implemented as shared registers,filling the registers to capacity can cause overflow to memory, whichcan call a trap or exception. In some embodiments, an overflow conditioncan be specified as a taint indication and accumulated for resourcemanagement.

Another technique for expanding send-and-receive communication morebroadly can comprise creating a message passing infrastructure inhardware. Speed is one advantage of forming the message passinginfrastructure in hardware. For example in the case of a system call,conventionally a slow operation, hardware can be configured to support asend instruction operable to check a bit in a channel selected for thesend operation to determine whether the channel is available and, ifnot, performing a system call by faulting to the system call. Thus, thehardware can be configured to pass execution through the operatingsystem in response to desired conditions.

In an example embodiment, the message passing infrastructure hardwarecan be configured to avoid passing execution through the operatingsystem, for example to avoid the context switch inherent with going tothe operating system. In another example embodiment, the hardware can beconfigured to include a message passing paradigm and one core can be runin ring 0 to enable access to operating system calls. The operatingsystem is not a separate process but rather a library call in a library.Another option is to allocate a hardware thread to the operating system.

The operating system performs a ring 0 call via a system call which, interms of hardware implementation, can be a function call to change abit, granting permission to change the bit, and identification of thestack from which the OS is operating. In one example implementation, theuser can explicitly control the stack, for example by placing theoperating system stack in a different register. In anotherimplementation, a system call can change the instruction pointer and thestack.

The message passing infrastructure hardware implementation can, forexample, include support for send and receive calls. The hardwareimplementation can enable faster operating speed. For particular specialcases, hardware send and receive calls can be faster than a sharedlibrary call. Send and receive are global messages, supportingpoint-to-point communication in two-party messaging. In someembodiments, the hardware implementation can support put and get APIs toenable sending a message to a designated address asynchronously orsynchronously, as selected. The designated address is in a globaladdress space partition, not local load-store. The put and get APIs canhandle access to shared physical memory by sending a request to themaster or server for the designated memory location. The memory ishashed across all the global memory space. In the illustrativeimplementation, get and put can be system calls rather thaninstructions, thus facilitating global access. Because the get and putsystem calls are relatively resource-expensive, efficiency can beattained by communicating blocks of data, for example 64K, at one timerather than for individual bytes.

For a cache-coherent shared memory that is accessed using the put andget system calls, different schemes can be used depending on whatentities are communicating. For entities which share memory, the get andput calls simply access the shared memory. For entities separated bysubstantial physical or network distances, the get and put calls, ifunable to fulfill the call by shared memory access, by running throughthe same router or similar local actions can send the calls to thenetwork interface to relay remotely, for example across the world. Forshared memory, whether cache-coherent or cache-noncoherent, the put andget, and send and receive operations are relatively simple since allentities can access the same memory. More complexity arises when memoryis not shared. In various embodiments, when memory is not shareddifferent schemes can be used such as copy-on-write (copying the sharedmemory), creating in remote memory the shared memory that shares thesame capability, an implicit in the put and get, or other options.

The message passing infrastructure thus can include hardware support forthe various put and get, send and receive, or the like system calls orinstructions. The message passing infrastructure can be configured toenable two threads to be forked and used with the put and get calls toenable optimum speed performance. The send and receive, and put and getinstructions, as described, consume two hardware threads or mightconsume two passive threads.

In some embodiments, the put-get and send-receive can be combined withaccess bits which designate memory to which the sender is allowedaccess. Passing along the access bits can enable a reduction in overheadwhile enabling protection across processes. The overhead of switching orsending a message drops significantly because the receiver already knowsthe memory to which the sender has access.

In some embodiments and/or applications, taints 105 can be applied tomemory 142 segregated by type to facilitate intrusion detection usingthe taint mechanism. Memory can thus be segregated into different typessuch as for code and data memory, or the like. Different types can havetaint mechanisms applied differently to the different types. Forexample, different memory types can have different levels ofgranularities, for example larger or smaller blocks of memory per taintvector. Also, different memory types can have more or fewer bits pertaint vector entry. Furthermore, different thresholds, decay rates, andthe like can be applied to different entries corresponding to differentmemory types.

In an example embodiment, a software model can be configured to use andenforce performance capabilities. In a relatively simple operation, ifpower is too low, then the software can limit the maximum number ofthreads or other capabilities. For example, in a cell processor case thenumber of threads can be limited to less than 1000. Fundamentally,software can disable functionality if sufficient power is unavailablefor scheduled operations.

In another example, a sensor or sensors can detect whether battery biasvoltage level is recovering too slowly or, similarly, a thermistor canindicate a battery is too hot which may indicate operating at tooaggressive a level. A bit or bits can be set indicating the recoverytime is too long. The set bit(s) can be used to throttle the maximumthread hopping rate in the case of a CPU with two threads. The bitsdisallow a thread hop and set an allowable rate of thread hopping; orperhaps allow thread hopping which creates slowing but saves power.

An example of performance capability monitoring and management can beimplemented in a CPU with four process threads each having instructionpointers. One of the four threads is selected to execute for nextinstruction cycle. Various types of information can be monitored todetermine which thread to select including recent demand for power,memory, CPU cycles, and the like. For example, a process can be aresource glutton and allocated fewer resources to enable other processespriority. Information is available relating to recent performance,requested performance, and acceptable performance (niceness).

Another option is to use a “NICE” instruction which can be used toadjust the priority level of predetermined instructions, enabling theinstructions to be run in the background at a convenient time. Forexample, if a processor or battery is running too hot, the NICEinstruction can reduce the urgency of executing code. In a particularexample implementation, the NICE instruction can change a multiplier andstep of a decay algorithm.

High and low capabilities can be specified. For example, a particularsoftware routine can sometimes, although rarely, use floating pointoperations so the capability for such routines can be set low.Operations performed by software can include monitoring, configuringparameters, and the like.

The electronic device 100 can be configured to manage or control variousaspects of operation. For example, in some embodiments the electronicdevice 100 can be operable to configure bit fields of the taint vector104 to include primary and secondary criteria corresponding to selectedtaint indicators 107 and to include information and/or identifiersrelating to actions, consequences, and usage.

Similarly, in some embodiments the electronic device 100 can be operableto configure the bit fields of the taint vector 104 to set a hierarchyof suspicion based on source, type, and/or identity of an event.

In some embodiments, the electronic device 100 can be constructed tomanage taints passed via network such as the Internet. For example, theelectronic device 100 can be operable to receive taint indicators 107from a tagged system call associated with accessing information from aweb page wherein an operating system injects a label indicatingorigination from a browser at an identified site.

The electronic device 100 can be arranged in some embodiments and/orunder specified conditions to monitor taints on the basis of source orevent which originates data, rather than aspects of the data itself,such that the electronic device 100 is operable to configure bit fieldsof the taint vector 104 to include tolerances based on questionabilityof a source and/or event.

The electronic device 100 can be constituted to segregate memory in avariety of ways. For example, in some embodiments the electronic device100 can be operable to configure a taint vector 104 to segregate memoryby type.

In particular embodiments, as selected, the electronic device 100 can beoperable to configure a taint vector 104 to segregate memory by type ata selected granularity.

Similarly, some embodiments of the electronic device 100 can be operableto configure a taint vector 104 to segregate memory between program codememory and data memory.

In various embodiments, taint indicators 107 and taint notifications canbe generated from any suitable source including either software,hardware, or other components and devices of electronic device 100, orfrom any source remote from the electronic device 100 such as a network,other systems connected to the network, and the like. In a particularexample, the electronic device 100 can be operable to track taints 105using hardware devices and insert initial taint notifications usingsoftware components.

In some embodiments, the electronic device 100 can be operable todynamically adjust rate and period of updating the taint vector 104using a taint adjustment vector comprising at least one parameter.

Similarly, the electronic device 100 can be operable to automaticallydecrement a set of rates using at least one timer, and apply at leastone parameter of a taint adjustment vector to the taint vector 104 uponexpiration of the at least one timer.

In various embodiments and/or conditions, the electronic device 100 canbe operated to ignore events that may or may not indicate potentialintrusion wherein the electronic device 100 can be operable to determinewhether to ignore one or more taint indicators 107, and to logoccurrences of the ignored one or more taint indicators 107 in an ignoreproblems taint vector.

Capabilities can be used to implement security. Typically, a system hasonly a few predetermined capabilities. However, a system can beconfigured in which every memory addressing register is assigned acapability. If the register specifies a capability to access theassociated memory location, the location can be accessed. Otherwise,access is prohibited, for example producing a fault or incrementing acounter or accumulator, such as a taint accumulator, which can be notedin an intrusion vector. For any aspect related to security, if a test isfailed, the counter is incremented and placed in the intrusion vector.

An instruction can be specified in an instruction set which sets acapability. In various embodiments, the instruction can be implementedin software, hardware, the operating system, or the like. Theinstruction can operate in association with a capabilities vector. Insome embodiments, the instruction can also or otherwise operate inassociation with a hint vector.

The capabilities vector can be associated with a pointer, an address,and an object. A highly basic capability is a lower bound and an upperbound. Other more complex capabilities can be implemented. In variousimplementations, the capabilities vector and the entitlement vector canbe separate, or can be combined. Merging the capabilities vector and theentitlement vector enables software structuring.

The capabilities vector can be used to enable fine-grained permission.Fine-grained permission facilitates operations of multiple users orentities in a shared memory data base, enabling the multiple users toaccess storage such as disk and to perform system calls, but limitaccess to data only to the user who owns the data or is authorized toaccess the data. Another benefit of fine-grained permissions is anability to facilitate and improve security while multiplexing softwarethreads onto hardware threads. In an example configuration, 64000software threads are multiplexed onto only four hardware threads. Only asmall portion of the software threads are running at one time with theremaining software threads idle. The software threads alternately run onthe hardware threads, then go back to idle to allow other softwarethreads to run.

A classic security hole in a database management is the inability tolimit access to data for the different software threads multiplexed ontothe hardware threads. A database typically does not allocate a hardwarethread to a user. In typical database operation, a request is receivedand placed on a software thread so that users are multiplexed onto thesoftware threads, an action giving very little protection. Betterprotection is attained by allocating each user to a separate process, atechnique that is prohibitively expensive because the threads areexpensive. Multiplexing the users onto software threads leaves asecurity hole because access to a particular user's data allowed whilerunning the user's software thread on a hardware thread is not removedwhen the user's software thread is swapped out from the hardware thread.The access permission remains so access remains enabled. The depictedsystem solves the security hole by using capabilities.

In a non-capabilities system, any of the software threads can access theentire database at any time, including any data that has been placed inshared memory (unless a call out is made through the operating system toenable any of the threads to create I/O, a prohibitively expensiveoperation). Simple databases only have one peer thread so all threadscan access any data. Many typical databases have 64 threads that canaccess any data in shared memory but only four threads that can accessI/O. These systems sometimes have different privilege levels (forexample, Intel's rings 0, 1, 2, 3) so specify compatibility. Most coderuns in ring 3 and the kernel in ring 0. Rings 1 and 2 are generally notused although several databases have features that can run in ring 1 andring 2 but are rare and used primarily for benchmarks (a benchmarkhack).

In an example implementation that uses capabilities, generally aprocessor has 16 or 32 registers, some of which are addressingregisters. A capability can be loaded to enable access to selectedthreads. A capability can be loaded to access a particular thread (ownedby another user) into hardware thread 0, enabling running as that user.This is one type of context switch—to change the software thread that isexecuting on hardware thread 0. The capability registers can then bechanged, a minor context switch and a change in privilege level. Theaction does not invalidate translation lookaside buffer (TLBs), butrather moves the permissions out of the TLB. The access control model isalso changed. Capabilities can be used in this manner to changeoperations, guaranteeing only access to data and/or resources for whichaccess is allowed by a permission-granting entity. Capabilities canguarantee a transitive exposure of only the data and/or resources ofanother user according to granted authorization. The technique isdeterministic so that, by inspection, which accesses are possible isknown.

Intrusion detection can use the concept of capabilities to implementfine-grained security.

Entitlements can be monitored using taint accumulation. Entitlements canbe used to allocate resources. Entitlements can be defined asuser-specified rights wherein a process is entitled to a predeterminedpercentage of power or of time. A scheduler or chooser can monitorentitlement values and schedule the next highest priority process. Aparticular scheme can allocate modulo by bit to avoid starving a processwith lower entitlement. In some conditions, the level of entitlement canbe overridden or adjusted. Entitlement can be set according to apredetermined algorithm which defines a “fair share” for the processes,for example round-robin, history-based, randomized, and the like, whichare efficient since a large history need not be accumulated. Thus, anefficient and inexpensive hardware implementation is possible. In someembodiments, a request for resources can be treated as a taint indicatorand accumulated using a taint accumulator or taint vector to determinehow to allocate among processes.

A metric can be specified which enables modification of a goal. Aselected level of entitlement to resource consumption can be assigned toeach process. One example scheme can be a short, low complexity methodwhich is implemented while storing a limited operation history. Forexample, when running low on battery charge, a sequence 1-2-3-4-4-3-2-1can be used to determine whether any of the processes is a resourceglutton and can rank the processes on order of gluttony. The mostgluttonous can be assigned the lowest priority. Another option can rankprocesses according to gluttony in combination with another factor ofgoodness (niceness). Processes can be ranked for the next cycle with themost gluttonous given last priority or can be ranked according togluttony and one other nice system criterion. Monitoring and/or controlcan be performed highly efficiently if hardware, although eithermonitoring can be performed either in hardware or software in variousembodiments. Power management units in CPUs can be used for monitoring,for example to monitor for increases or decreases in voltage orfrequency, and for thread execution selection.

Capabilities can be used to perform monitoring and allocation ofresources. For example, granting the capability to run video processingsoftware can be combined with simultaneous granting of power capability.

Power is typically global to a process or to an individual CPU. Use ofcapabilities enables more refined control of power, for example powercan be made specific to an object or library routine. With power globalto a process, the process will continue to run in absence of a fault, apage fault, a disk access, or the like, and will run until blocked bythe operating system scheduler, allowing high power consumption. Use ofcapabilities enables power to be controlled on a per-hardware threadgranularity. Use of capabilities further enables power to be controlledspecific to a per-hardware thread granularity for throttling power.

Processors can use instruction prefetch to improve execution speed byreducing wait states. The processor prefetches an instruction by requestfrom main memory before the instruction is needed and, when retrievedfrom memory, placing the prefetched instruction in a cache. When needed,the instruction is quickly accessed from the cache. Prefetch can be usedin combination with a branch prediction algorithm which anticipatesresults of execution to fetch predicted instructions in advance.Prefetches conventionally operate independently. In some embodiments, aprocessor disclosed herein can prefetch according to holistic monitoringof operating conditions such as voltage, frequency, and the like to moreaccurately determine or predict which instructions to prefetch.

The cache can be reconfigured dynamically, for example beginning with asingle large, slow cache which can be divided into a relatively smallsubcache and a larger subcache to enable faster operation. Inembodiments disclosed herein, operating characteristics can be monitoredto generate information for dynamic reconfiguring of the cache. In someembodiments, cache phenomena such as cache hits and misses can behandled as taint indicators for taint accumulation, for example using ataint vector, to facilitate handling of the cache. As a result of themonitored operating conditions, the cache can be selectively configuredfor slower or faster speed, larger and smaller cache subregions. In someconditions, part of the cache can be temporarily disabled, for exampleto save power. Monitoring of operating conditions can enable a suitablebalance of considerations to determine whether part of the cache is tobe disabled, for example determining whether the power saved indisabling part of the cache is appropriate in light of the power lostwith a greater cache miss rate.

Disclosed system and method embodiments can use operating conditionmonitoring and holistic control at the level of calling an object. In anobject-level paradigm, various objects or values (such as numbers,symbols, strings, and the like) can be combined to form other objects orvalues until the final result objects or values are obtained. New valuescan be formed from existing values by the application of variousvalue-to-value functions, such as addition, concatenation, matrixinversion, and the like. Various objects have different impacts onsystem operations.

An example of an object which, when called, can have large consumptionof power or other resources is video encoding which is a brute force,unintelligent algorithm which runs much more efficiently on dedicatedhardware than a general CPU, and has real-time constraints. Videoconferencing has similar real-time constraints.

Another object example is video games which perform many different tasksconcurrently including processing geometry and processing videosimultaneously, possibly processing speech for Skype communications,voice compression, input/output, and the like. Video games thustypically involve concurrent operation of multiple objects such as thegame processing tasks and interface (Application Programming Interface,API) that perform different actions separately. The multiple objects arecommonly run as separate threads, unless prohibitive due to the largeamount of overhead in running threads that are not essential. Separatethreads simplify programming.

In some configurations, applications, and conditions, multiple threadscan be run wherein the threads need not be run in the same context.

Hyperthreading is a particular implementation of hardware threading.Software threading is a slightly different implementation of threadingwherein the threads are often, but not always, related. In someimplementations, a processor can include a GOAL register that can beused to set performance characteristics for particular threads. Forexample, if different routines (Skype, physics) are run in differentthreads, selected operating characteristics for the threads can beloaded into the GOAL register to give the threads separate issues.Allocating priority to the different threads can be difficult. In anillustrative system, priority to the threads can be allocated using aNICE utility which specifies acceptable performance for a particularoperation and allows reduced priority in appropriate conditions fortasks that can be assigned lower priority with little or no consequence.

In an example implementation, priorities, particular types ofpriorities, and entitlements can be associated with particular libraryroutines to facilitate management of relatively heuristic phenomena. Alibrary can be constituted wherein entitlements are assigned toindividual library routines. The library includes information foradjusting the priority of threads, for example by identifying aphenomenon as a taint indication and accumulating taint indications. Insome configurations or applications, the library can support hintvectors, such as branch prediction hints to specify whether staticprediction should be taken or not taken. In some embodiments, thelibrary can be configured to support NICE-type handling of a hintvector.

A process scheduler can be constituted to support prioritizedentitlements and resource allocations upon calling selected libraries. Atypical embodiment includes such support in software, although hardwaresupport can also be implemented. For example, a network library caninclude library routines adapted for heavy network usage so thatresources giving access to the network are more important processes toschedule. More entitlements are allocated to network-related resources.Libraries can also be configured to handle secondary priorities thatchange dynamically. For example, a sound card can have a greater powerpriority and have a pattern of operation wherein a process uses anetwork card and possibly other subsystems in combination with the soundcard. Thus, the network card and other subsystems can also be allocateda higher priority. Similarly, for a process which performs less modelingand number computation in lieu of higher input/output operations andsending of information, a higher level of priority can be allocated toinput/output resources.

Entitlements can be used to specify operations of a library. Forexample, a library with entitlement to run a predetermined number offloating point operations per second can, in response to a condition ofexecuting instructions with few or no floating point computations, usethe condition as a hint to power down floating point hardware, thussaving power. Thus, if computations include fixed point operations butno floating point operations, an a priori indicator can be generateddesignating that the floating point hardware is not needed in the nearfuture and can be powered down. A process can call a library and, ifknown that a resource is not needed, the resource can be temporarilyhalted, thereby changing the entitlement level of that process withrespect to the resource (for example a floating point unit) to a verylow point.

In the illustrative example, the entitlement level of the process withrespect to the floating point unit can be changed to very low becausethe resource is not needed for a foreseeable duration. The process thusindicates to other processes a willingness to relinquish access to thesource, for example a willingness to be “nice” about allowing others touse the resource, so that access is deferred in favor of any otherprocess that uses the resource, or the resource is shut down if notcurrently needed by another process.

Rather than have hardware determine demand for a resource afterinstructions have been executed, the illustrative system and method canuse a call to a library or the result of making a call to the library asan indicator of entitlement niceness. This entitlement can be enforcedin the manner of capabilities, for example by requesting access to amemory region, a request which may be denied. The library can giveinformation regarding entitlement, thus giving a priori knowledge.

Resource allocation can also be managed using hints. An illustrativeinstruction that uses a hint is a hint that not much floating pointcomputation is to be performed, a hint indicative of power demand. Forexample, hints to maintain power at a low level or to maintain power ata high level. An exception can create problems when using hints, since ahint is not unwound in the event of an exception. For example, for ahint to maintain high power, an exception which changes the conditionbut does not reset the hint allows hardware to remain in a high powermode, potentially forever. Examples of problems with hint processing inconditions of context switching include problems with unlocking memorylocations.

In contrast to entitlements, capabilities enable mechanisms to unwind.

Entitlement Vector can be used as part of or in affiliation with taintaccumulation or a taint vector for managing resources. An entitlementvector can have multiple fields, for example including floating point,power, arithmetic logic unit (ALU), graphics triangle including anysuitable entitlements, translation lookaside buffers TLBs, virtualmemory usage, and the like. The entitlement vector can thus be used, forexample, to power down the TLB as no longer relevant to operation, or toenable usage of a wide range of virtual memory.

Another field of the entitlement vector can specify scale. Examples ofscale can be human scale, width of the accumulator, or any suitablescale. For example, for a finger print, a suitable scale can be no morethan 2 MB.

A further field of the entitlement vector can be data path width, asimilar concept to scale. A large instruction size, for example 1024bits, wastes power, but typically only a portion of the bits are used atone time so that a desired subset of the bits can be activated, changingthe data path width. The scale concept leads to the concept of aselected partial data path width. The data path width is part of theentitlement. For example, of 1024 bits logic can compute the number ofbits actually needed and allocate that predetermined subset of bits,such as 128 bits. The data path field thus can be used to lower the datapath width used of the available entitlement vector width, for exampleactivating a super-accumulator data path width.

Referring to FIGS. 2A through 2U, schematic flow diagrams depict anembodiment or embodiments of a method operable in a computing deviceadapted to manage security risk by accumulating and monitoring taintindications, and responding to predetermined security risks by trapping.An embodiment of a method 200 operable in a computing device forhandling security risk, shown in FIG. 2A, can comprise receiving 201 aplurality of taint indicators corresponding to at least one of aplurality of taints indicative of potential security risk and injectedfrom at least one of a plurality of resources, and tracking 202 theplurality of taints.

Taints can be selected, for example, from one or more circumstances orphenomena including a null pointer reference, an attempt to access asecured part of a processor, an attempt to access a secured resource, abuffer overrun, and an event originating in a region that raisessuspicion. Other example taints can include a fault, an integeroverflow, a plurality of taint indicators that exceeds at least onepredetermined threshold, a taint indicated by power law analysis, ataint indicated by a race function, and an attempt to access a key, anda variety of other circumstances or phenomena.

The plurality of taints comprise one or more of a plurality of distinctclasses comprising a plurality of distinct affiliates, systemcharacteristics, sources, events, activities, and/or conditions.

In some embodiments, as depicted in FIG. 2B, a method 205 can furthercomprise receiving 206 at least one taint indicator from a tagged systemcall associated with accessing information from a web page wherein anoperating system injects a label originating from a browser at anidentified site.

In some embodiments, as shown in FIG. 2C, a method 207 can beimplemented which further comprises injecting 208 at a hardwarecomponent at least one taint of the plurality of taints when the atleast one taint is known a priori to indicate an event and/or conditionis suspicious.

Referring to FIG. 2D, embodiments of a method 210 for handling securityrisk can further comprise indicating 211 potential security riskoriginating from at least one of the plurality of resources by at leastone taint of the plurality of taints, allocating 212 the at least onetaint of the plurality of taints in at least one taint vector, andtracking 213 the at least one taint in at least one taint vector. Themethod 210 can further comprise monitoring 214 the at least one taintvector, and detecting 215 a predetermined taint condition wherein apredetermined condition of data is indicated.

In some embodiments, one or more of the at least one taint vector cancomprise a composite taint vector that correlates a taint source and ataint activity type.

In various embodiments and/or conditions, illustrated in FIG. 2E, themethod 220 can further comprise indicating 221 potential security riskoriginating from at least one of the plurality of resources by at leastone taint of the plurality of taints, and allocating 222 the at leastone taint of the plurality of taints in at least one taint vector. Themethod 220 can further comprise tracking 223 the at least one taint inat least one taint vector, and incrementing 224 the at least one taintvector upon detection of a predetermined taint condition wherein apredetermined condition of data is indicated.

In some embodiments, as depicted in FIG. 2F, a method 225 can furthercomprise indicating 226 potential security risk originating from atleast one of the plurality of resources by at least one taint of theplurality of taints, listing 227 the at least one taint of the pluralityof taints in at least one taint vector, and responding 228 to apredetermined taint condition.

In various embodiments and/or applications, shown in FIG. 2G, a method230 can further comprise monitoring 231 the plurality of taints,creating 232 a trust profile based on the monitoring, and trapping 233to a software process based at least partly on determination of asuspicious condition.

Various methods can involve monitoring of an aspect of tainting andresponding to a monitored event. For example as illustrated in FIG. 2H,a method 235 can further comprise monitoring 236 the plurality of taintsin network input/output operations, and trapping 237 to a softwareprocess based at least partly on determination of a network input/outputcondition of an attempt of malware to communicate to a malware operator.

In a further example embodiment of a method 240 for tracking taints andresponding to a taint event, shown in FIG. 2I, a method 240 can furthercomprise monitoring 241 the plurality of taints using a hardware device,and inserting 242 initial taint notifications using a software process.

Referring to FIG. 2J, a method 245 can further comprise responding 246to at least one security risk event with at least one response selectedfrom a group of responses. A variety of responses can be performed,depending on criticality of a particular taint condition. Some responsesare relatively minor for taint conditions that are assessed to besomewhat benign. Minor responses can include, among others, ignoring theat least one security risk event, logging the at least one security riskevent, displaying a notification, displaying a warning message, andgenerating an alarm. Other response can affect operations andfunctionality while allowing actions to continue including, for example,preventing a memory and/or register write, modifying operatingfrequency, modifying operating voltage, modifying an operatingparameter, and the like. More aggressive responses can be invoked forrelatively critical taint conditions such as, among others, performing asystem call, calling a trap and/or exception, terminating operation ofselected resources, and activating a system shutdown.

As shown in FIG. 2K, in various embodiments and/or in variousconditions, a method 247 can further comprise accumulating 248 aplurality of taint indicators indicative of potential security risk froma plurality of distinct sources at distinct times in ones of the atleast one taint vector.

Similarly, as depicted in FIG. 2L, a method 250 can further compriseaccumulating 251 the plurality of taint indicators independently usingones of the plurality of accumulation functions selected from severalpossible functions. The accumulation functions can include comparingones of the accumulated plurality of taint indicators to at least onepredetermined threshold, performing power law analysis, performing arace function, performing a counting function, and the like. Suitablecounting functions can include counting the number of taints, countingthe number of taints per memory unit, counting the number ofinstructions tainted, counting the number of tainted instructions,counting the number of instructions written as a result of a taint,counting the number of data loads and stores, counting the number ofmemory accesses, counting the number of calls, counting the number ofreturns, counting the number of branches, counting the number of integeroverflows, counting the number of network input/output events, countingthe number of null pointer references, counting the number of bufferoverruns/overflows, counting the number of repeated attempts to access akey, and the like.

Similarly, referring to FIG. 2M, a method 252 can further compriseallocating 253 taints at a selected granularity. Examples of suitablelevels of granularity can include allocating taints by memory page,allocating taints by byte, allocating taints by word, allocating taintsby memory block, and allocating taints by hardware process identifier(PID). Other selected granularities can include allocating taints toenable a cross-thread taint, allocating taints among hardware devices,allocating taints by component, allocating taints by software component,and the like.

Referring to FIG. 2N, a method 255 of handling security can furthercomprise acquiring 256 a history of the ones of the at least one taintvector in a feedback loop that correlates taints with responses to thetaints.

As shown in FIG. 2O, a method 257 can further comprise applying 258 atleast one function to the at least one entry of the at least one taintvector. In various example embodiments and/or conditions, the at leastone function can be selected from various functions such as weights,masks, sums, combinations, arithmetic functions, logical operations,transforms, and the like.

Taints for various resources can be located in different places,organized in various manners among different memory locations or types,and/or associated with different amounts of memory. Hence, referring toFIG. 2P, the method 260 can further comprise injecting 261 selected onesthe plurality of taints by the plurality of resources of a groupincluding physical and/or logical instances of processors, centralprocessing units (CPUs), graphics hardware, network controllers, memory,memory management, hardware, microarchitecture, sound cards, videocards, network interfaces, instruction set architecture (ISA), librarycalls, library functions, software objects, compilers, operatingsystems, and the like.

Furthermore, as shown in FIG. 2Q, a method 262 can further compriseinjecting 263 ones of the plurality of taints from a resource of theplurality of resources that is remote from an electronic device, andcommunicating 264 at least one taint indicator corresponding to theinjected ones of the plurality of taints to the electronic device.

Likewise, as illustrated in FIG. 2R, a method 265 can further compriseinjecting 266 ones of the plurality of taints from remote software thatis remote from an electronic device, and communicating 267 at least onetaint indicator corresponding to the injected ones of the plurality oftaints to the electronic device.

Referring to FIG. 2S, a method 270 of handling security risk can furthercomprise injecting 271 ones of the plurality of taints from a resourceof the plurality of resources that is locally coupled to an electronicdevice, and directly accessing 272 at least one taint indicatorcorresponding to the injected ones of the plurality of taints by theelectronic device.

Similarly, as shown in FIG. 2T, a method 275 of handling security riskcan further comprise injecting 276 ones of the plurality of taints bylocal software that is local to an electronic device, and directlyaccessing 277 at least one taint indicator corresponding to the injectedones of the plurality of taints by the electronic device.

The method can be used as at least part of a federated system which canbe implemented in an infrastructure such as an architecture includingservers and clients. Accordingly, as depicted in FIG. 2U, a method 280can further comprise allocating 281 an entry of one or more of the atleast one taint vector to selected ones of the plurality of resources,and federating 282 taints of the selected ones of the plurality ofresources to the entry.

Referring to FIGS. 3A, 3B, and 3C, embodiments comprise a computerprogram product 300 adapted to manage security risk by accumulating andmonitoring taint indications. The computer program product includes acomputer-readable storage medium 306 bearing program instructions. Theprogram instructions are operable to perform a process in a computingdevice. The computer program product can be constituted as anycombination of one or more computer usable or computer readablemedium(s), for example but not limited to, communication, electronic,semiconductor, magnetic, optical, electromagnetic, infrared, in the formof propagation medium, system, apparatus, device, or the like. Specificexamples of the computer-readable medium may include, are not limitedto, a wired connection, a wireless connection, Internet or an intranettransmission media, an optical fiber, a magnetic storage device, aportable diskette, a hard disk, a portable compact disc read-only memory(CDROM), an optical storage device, a random access memory (RAM), aread-only memory (ROM), an erasable programmable read-only memory(EPROM), Flash memory, or the like. Similarly, the computer-usable orcomputer-readable medium can be a visual display such as paper, poster,screen view, that can be visually or electronically captured such as byoptical scanning of a medium, then compiled, interpreted, or otherwiseprocessed.

As shown in FIG. 3A, the program instructions can comprise programinstructions 310 operable to receive a plurality of taint indicatorscorresponding to at least one of a plurality of taints indicative ofpotential security risk and injected from at least one of a plurality ofresources. The computer program product 300 can further comprise programinstructions 312 operable to track the plurality of taints.

In some embodiments, the computer program product 300 can furthercomprise program instructions 314 operable to receive at least one taintindicator from a tagged system call associated with accessinginformation from a web page wherein an operating system injects a labeloriginating from a browser at an identified site.

In various embodiments and/or applications, the computer program product300 can further comprise program instructions 316 operable to inject ata hardware component at least one taint of the plurality of taints whenthe at least one taint is known a priori to indicate an event and/orcondition is suspicious.

Further embodiments of the computer program product 300 can furthercomprise program instructions 318 operable to indicate potentialsecurity risk originating from at least one of the plurality ofresources by at least one taint of the plurality of taints, programinstructions 320 operable to allocate the at least one taint of theplurality of taints in at least one taint vector, and programinstructions 322 operable to track the at least one taint in at leastone taint vector.

Similarly, the computer program product 300 can further comprise programinstructions 324 operable to monitor the at least one taint vector,program instructions 326 operable to track the at least one taint in atleast one taint vector, program instructions 328 operable to incrementthe at least one taint vector upon detection of a predetermined taintcondition wherein a predetermined condition of data is indicated, andprogram instructions 330 operable to detect a predetermined taintcondition wherein a predetermined condition of data is indicated.

As shown in FIG. 3B, the program instructions can comprise programinstructions 332 operable to monitor the plurality of taints, programinstructions 334 operable to monitor the plurality of taints in networkinput/output operations, and program instructions 336 operable tomonitor the plurality of taints using a hardware device for taintnotifications inserted using a software process. The computer programproduct 300 can further comprise program instructions 338 operable tocreate a trust profile based on the monitoring, and program instructions340 operable to acquire a history of the ones of the at least one taintvector in a feedback loop that correlates taints with responses to thetaints. The computer program product 300 can further comprise programinstructions 342 operable to trap to a software process based at leastpartly on determination of a suspicious condition, and programinstructions 344 operable to trap to a software process based at leastpartly on determination of a network input/output condition of anattempt of malware to communicate to a malware operator.

In various embodiments and/or applications, the computer program product300 can further comprise program instructions 346 operable to apply atleast one function to the at least one entry of the at least one taintvector, wherein the at least one function is selected from a groupconsisting of weights, masks, sums, combinations, arithmetic functions,logical operations, and transforms.

Referring to FIG. 3C, further embodiments of the computer programproduct 300 can further comprise program instructions 348 operableprogram instructions operable to inject ones of the plurality of taintsfrom a resource of the plurality of resources that is remote from anelectronic device, program instructions 350 operable to inject ones ofthe plurality of taints from remote software that is remote from anelectronic device, program instructions 352 operable to inject ones ofthe plurality of taints from a resource of the plurality of resourcesthat is locally coupled to an electronic device wherein the at least onetaint indicator corresponding to the injected ones of the plurality oftaints is directly accessing by the electronic device, and programinstructions 354 operable to inject ones of the plurality of taints bylocal software that is local to an electronic device wherein the atleast one taint indicator corresponding to the injected ones of theplurality of taints is directly accessed by the electronic device. Thecomputer program product 300 can further comprise program instructions356 operable to communicate at least one taint indicator correspondingto the injected ones of the plurality of taints to the electronicdevice.

Referring to FIGS. 4A, 4B, and 4C, schematic block diagrams illustrateembodiments of a computing system 400 adapted to manage security risk bymonitoring taint indications and responding to a determined taintcondition, for example by trapping. The computing system 400 cancomprise means 470 for receiving a plurality of taint indicators 407corresponding to at least one of a plurality of taints 405 indicative ofpotential security risk and injected from at least one of a plurality ofresources 402, and means 471 for tracking the plurality of taints 405.

In some embodiments, taints can originate from network users andresources. Accordingly, for example, the computing system 400 canfurther comprise means 472 for receiving at least one taint indicator407 from a tagged system call 422 associated with accessing informationfrom a web page 423 wherein an operating system 424 injects a label 425originating from a browser 426 at an identified site.

In various embodiments and/or conditions, taints can be injected fromhardware. Accordingly, the computing system 400 can further comprisemeans 473 for injecting at a hardware component 410 at least one taint405 of the plurality of taints 405 when the at least one taint 405 isknown a priori to indicate an event 416 and/or condition 420 issuspicious.

In further embodiments, the computing system 400 can further comprisemeans 474 for indicating potential security risk originating from atleast one of the plurality of resources 402 by at least one taint 405 ofthe plurality of taints 405, means 475 for allocating the at least onetaint 405 of the plurality of taints 405 in at least one taint vector404, means 476 for tracking the at least one taint 405 in at least onetaint vector 404, and means 477 for monitoring the at least one taintvector 404. In some embodiments, the computing system 400 can furthercomprise means 478 for tracking the at least one taint 405 in at leastone taint vector 404, means 479 for incrementing the at least one taintvector 404 upon detection of a predetermined taint condition 406 whereina predetermined condition of data is indicated, and means 480 fordetecting a predetermined taint condition 406 wherein a predeterminedcondition of data is indicated.

Referring to FIG. 4B, in several embodiments various techniques formonitoring taints can be implemented. Accordingly, the computing system400 can further comprise means 481 for monitoring the plurality oftaints 405, means 482 for monitoring the plurality of taints 405 innetwork 436 input/output operations, and means 483 for monitoring theplurality of taints 405 using a hardware device 409 for taintnotifications inserted using a software process 432. In some embodimentsand/or applications, the computing system 400 can further comprise means484 for creating a trust profile based on the monitoring, and means 485for acquiring a history of the ones of the at least one taint vector 404in a feedback loop that correlates taints 405 with responses to thetaints 405. In various embodiments, the computing system 400 can respondto a predetermined taint condition by trapping. For example, thecomputing system 400 can further comprise means 486 for trapping to asoftware process 432 based at least partly on determination of asuspicious condition, and means 487 for trapping to a software process432 based at least partly on determination of a network 436 input/outputcondition of an attempt of malware 437 to communicate to a malwareoperator 438.

In some embodiments and/or applications, the computing system 400 canfurther comprise means 488 for applying at least one function 444 to theat least one entry of the at least one taint vector 404, wherein the atleast one function 444 is selected from a group consisting of weights,masks, sums, combinations, arithmetic functions, logical operations, andtransforms.

Referring to FIG. 4C, in various embodiments, taints can be injectedfrom diverse sources. For example, the computing system 400 can furthercomprise means 489 for injecting ones of the plurality of taints 405from a resource 402 of the plurality of resources 402 that is remotefrom an electronic device 401, means 490 for injecting ones of theplurality of taints 405 from remote software 462 that is remote from anelectronic device 401, means 491 for injecting ones of the plurality oftaints 405 from a resource 402 of the plurality of resources 402 that islocally coupled to an electronic device 401 wherein the at least onetaint indicator 407 corresponding to the injected ones of the pluralityof taints 405 is directly accessing by the electronic device 401, means492 for injecting ones of the plurality of taints 405 by local software464 that is local to an electronic device 401 wherein the at least onetaint indicator 407 corresponding to the injected ones of the pluralityof taints 405 is directly accessed by the electronic device 401, and thelike. In some embodiments and/or conditions, the computing system 400can further comprise means 493 for communicating at least one taintindicator 407 corresponding to the injected ones of the plurality oftaints 405 to the electronic device 401.

In the detailed description herein, reference is made to theaccompanying drawings, which form a part hereof. In the drawings,similar symbols typically identify similar components, unless contextdictates otherwise. The illustrated embodiments described in thedetailed description, drawings, and claims are not meant to be limiting.Other embodiments may be utilized, and other changes may be made,without departing from the spirit or scope of the subject matterpresented here.

FIG. 5 and the following discussion are intended to provide a brief,general description of an environment in which embodiments may beimplemented. FIG. 5 illustrates an example system that includes acomputing device 520, which may be included in an electronic device thatalso includes a device functional element 550. For example, theelectronic device may include any item having electrical and/orelectronic components playing a role in a functionality of the item,such as a limited resource computing device, a wireless communicationdevice, a mobile wireless communication device, an electronic pen, ahandheld electronic writing device, a digital camera, a scanner, anultrasound device, an x-ray machine, a non-invasive imaging device, acell phone, a PDA, a Blackberry® device, a printer, a refrigerator, acar, and an airplane. The computing device 520 can include a processingunit 521, a system memory 522, and a system bus 523 that couples varioussystem components including the system memory 522 to the processing unit521. The system bus 523 may be any of several types of bus structuresincluding a memory bus or memory controller, a peripheral bus, and alocal bus using any of a variety of bus architectures. The system memoryincludes read-only memory (ROM) 524 and random access memory (RAM) 525.A basic input/output system (BIOS) 526, containing the basic routinesthat help to transfer information between sub-components within the thincomputing device 520, such as during start-up, is stored in the ROM 524.A number of program modules may be stored in the ROM 524 and/or RAM 525,including an operating system 528, one or more application programs 529,other program modules 530 and program data 531.

A user may enter commands and information into the computing device 520through input devices, such as a number of switches and buttons,illustrated as hardware buttons 544, connected to the system via asuitable interface 545. Input devices may further include atouch-sensitive display with suitable input detection circuitry,illustrated as a display 532 and screen input detector 533. The outputcircuitry of the touch-sensitive display 532 is connected to the systembus 523 via a video driver 537. Other input devices may include amicrophone 534 connected through a suitable audio interface 535, and aphysical hardware keyboard (not shown). Output devices may include atleast one the display 532, or a projector display 536.

In addition to the display 532, the computing device 520 may includeother peripheral output devices, such as at least one speaker 538. Otherexternal input or output devices 539, such as a joystick, game pad,satellite dish, scanner or the like may be connected to the processingunit 521 through a USB port 540 and USB port interface 541, to thesystem bus 523. Alternatively, the other external input and outputdevices 539 may be connected by other interfaces, such as a parallelport, game port or other port. The computing device 520 may furtherinclude or be capable of connecting to a flash card memory (not shown)through an appropriate connection port (not shown). The computing device520 may further include or be capable of connecting with a networkthrough a network port 542 and network interface 243, and throughwireless port 546 and corresponding wireless interface 547 may beprovided to facilitate communication with other peripheral devices,including other computers, printers, and so on (not shown). It will beappreciated that the various components and connections shown areexamples and other components and means of establishing communicationslinks may be used.

The computing device 520 may be primarily designed to include a userinterface. The user interface may include a character, a key-based,and/or another user data input via the touch sensitive display 532. Theuser interface may include using a stylus (not shown). Moreover, theuser interface is not limited to an actual touch-sensitive panelarranged for directly receiving input, but may alternatively or inaddition respond to another input device such as the microphone 534. Forexample, spoken words may be received at the microphone 534 andrecognized. Alternatively, the computing device 520 may be designed toinclude a user interface having a physical keyboard (not shown).

The device functional elements 550 are typically application specificand related to a function of the electronic device, and is coupled withthe system bus 523 through an interface (not shown). The functionalelements may typically perform a single well-defined task with little orno user configuration or setup, such as a refrigerator keeping foodcold, a cell phone connecting with an appropriate tower and transceivingvoice or data information, and a camera capturing and saving an image.

FIG. 6 illustrates an example embodiment of a general-purpose computingsystem in which embodiments may be implemented, shown as a computingsystem environment 600. Components of the computing system environment600 may include, but are not limited to, a computing device 610 having aprocessing unit 620, a system memory 630, and a system bus 621 thatcouples various system components including the system memory to theprocessing unit 620. The system bus 621 may be any of several types ofbus structures including a memory bus or memory controller, a peripheralbus, and a local bus using any of a variety of bus architectures. By wayof example, and not limitation, such architectures include IndustryStandard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus,Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA)local bus, and Peripheral Component Interconnect (PCI) bus, also knownas Mezzanine bus.

The computing system environment 600 typically includes a variety ofcomputer-readable media products. Computer-readable media may includeany media that can be accessed by the computing device 610 and includeboth volatile nonvolatile media, removable and non-removable media. Byway of example, and not of limitation, computer-readable media mayinclude computer storage media and communications media.

Computer storage media includes volatile and nonvolatile, removable andnon-removable media implemented in any method or technology for storageof information such as computer-readable instructions, data structures,program modules, or other data. Computer storage media includes, but isnot limited to, random-access memory (RAM), read-only memory (ROM),electrically erasable programmable read-only memory (EEPROM), flashmemory, or other memory technology, CD-ROM, digital versatile disks(DVD), or other optical disk storage, magnetic cassettes, magnetic tape,magnetic disk storage, or other magnetic storage devices, or any othermedium which can be used to store the desired information and which canbe accessed by the computing device 610. In a further embodiment, acomputer storage media may include a group of computer storage mediadevices. In another embodiment, a computer storage media may include aninformation store. In another embodiment, an information store mayinclude a quantum memory, a photonic quantum memory, and/or atomicquantum memory. Combinations of any of the above may also be includedwithin the scope of computer-readable media.

Communications media may typically embody computer-readableinstructions, data structures, program modules, or other data in amodulated data signal such as a carrier wave or other transportmechanism and include any information delivery media. The term“modulated data signal” means a signal that has one or more of itscharacteristics set or changed in such a manner as to encode informationin the signal. By way of example, and not limitation, communicationsmedia include wired media, such as a wired network and a direct-wiredconnection, and wireless media such as acoustic, RF, optical, andinfrared media.

The system memory 630 includes computer storage media in the form ofvolatile and nonvolatile memory such as ROM 631 and RAM 632. A RAM mayinclude at least one of a DRAM, an EDO DRAM, a SDRAM, a RDRAM, a VRAM,and/or a DDR DRAM. A basic input/output system (BIOS) 633, containingthe basic routines that help to transfer information between elementswithin the computing device 610, such as during start-up, is typicallystored in ROM 631. RAM 632 typically contains data and program modulesthat are immediately accessible to or presently being operated on byprocessing unit 620. By way of example, and not limitation, FIG. 6illustrates an operating system 634, application programs 635, otherprogram modules 636, and program data 637. Often, the operating system634 offers services to applications programs 635 by way of one or moreapplication programming interfaces (APIs) (not shown). Because theoperating system 634 incorporates these services, developers ofapplications programs 635 need not redevelop code to use the services.Examples of APIs provided by operating systems such as Microsoft's“WINDOWS” are well known in the art.

The computing device 610 may also include other removable/non-removable,volatile/nonvolatile computer storage media products. By way of exampleonly, FIG. 6 illustrates a non-removable non-volatile memory interface(hard disk interface) 640 that reads from and writes for example tonon-removable, non-volatile magnetic media. FIG. 6 also illustrates aremovable non-volatile memory interface 650 that, for example, iscoupled to a magnetic disk drive 651 that reads from and writes to aremovable, non-volatile magnetic disk 652, and/or is coupled to anoptical disk drive 655 that reads from and writes to a removable,non-volatile optical disk 656, such as a CD ROM. Otherremovable/nonremovable, volatile/non-volatile computer storage mediathat can be used in the example operating environment include, but arenot limited to, magnetic tape cassettes, memory cards, flash memorycards, DVDs, digital video tape, solid state RAM, and solid state ROM.The hard disk drive 641 is typically connected to the system bus 621through a non-removable memory interface, such as the interface 640, andmagnetic disk drive 651 and optical disk drive 655 are typicallyconnected to the system bus 621 by a removable non-volatile memoryinterface, such as interface 650.

The drives and their associated computer storage media discussed aboveand illustrated in FIG. 6 provide storage of computer-readableinstructions, data structures, program modules, and other data for thecomputing device 610. In FIG. 6, for example, hard disk drive 641 isillustrated as storing an operating system 644, application programs645, other program modules 646, and program data 647. Note that thesecomponents can either be the same as or different from the operatingsystem 634, application programs 635, other program modules 636, andprogram data 637. The operating system 644, application programs 645,other program modules 646, and program data 647 are given differentnumbers here to illustrate that, at a minimum, they are differentcopies.

A user may enter commands and information into the computing device 610through input devices such as a microphone 663, keyboard 662, andpointing device 661, commonly referred to as a mouse, trackball, ortouch pad. Other input devices (not shown) may include at least one of atouch sensitive display, joystick, game pad, satellite dish, andscanner. These and other input devices are often connected to theprocessing unit 620 through a user input interface 660 that is coupledto the system bus, but may be connected by other interface and busstructures, such as a parallel port, game port, or a universal serialbus (USB).

A display 691, such as a monitor or other type of display device orsurface may be connected to the system bus 621 via an interface, such asa video interface 690. A projector display engine 692 that includes aprojecting element may be coupled to the system bus. In addition to thedisplay, the computing device 610 may also include other peripheraloutput devices such as speakers 697 and printer 696, which may beconnected through an output peripheral interface 695.

The computing system environment 600 may operate in a networkedenvironment using logical connections to one or more remote computers,such as a remote computer 680. The remote computer 680 may be a personalcomputer, a server, a router, a network PC, a peer device, or othercommon network node, and typically includes many or all of the elementsdescribed above relative to the computing device 610, although only amemory storage device 681 has been illustrated in FIG. 6. The networklogical connections depicted in FIG. 6 include a local area network(LAN) and a wide area network (WAN), and may also include other networkssuch as a personal area network (PAN) (not shown). Such networkingenvironments are commonplace in offices, enterprise-wide computernetworks, intranets, and the Internet.

When used in a networking environment, the computing system environment600 is connected to the network 671 through a network interface, such asthe network interface 670, the modem 672, and/or the wireless interface693. The network may include a LAN network environment, and/or a WANnetwork environment, such as the Internet. In a networked environment,program modules depicted relative to the computing device 610, orportions thereof, may be stored in a remote memory storage device. Byway of example, and not limitation, FIG. 6 illustrates remoteapplication programs 685 as residing on computer storage medium 681. Thenetwork connections shown are examples and other means of establishingcommunications link between the computers may be used.

In various embodiments and/or conditions, responding to security risk inresponse to detection of the at least one security risk event can be oneor more responses selected from a group of responses that range fromrelatively minor informational actions to actions which can moderatelyor substantially change system operations, or even terminate some or allsystem operations. Minor or informational responses can includeincluding ignoring the at least one security risk event, logging the atleast one security risk event, displaying a notification, displaying awarning message, generating an alarm, and the like. Responses affectingsystem operations can include preventing a memory and/or register write,modifying operating frequency, modifying operating voltage, modifyinganother operating parameter, performing a system call, and others. Moredrastic responses that can moderately or substantially affect operationscan include calling a trap and/or exception, terminating operation ofselected resources, activating a system shutdown, and the like.

Terms “substantially”, “essentially”, or “approximately”, that may beused herein, relate to an industry-accepted variability to thecorresponding term. Such an industry-accepted variability ranges fromless than one percent to twenty percent and corresponds to, but is notlimited to, materials, shapes, sizes, functionality, values, processvariations, and the like. The term “coupled”, as may be used herein,includes direct coupling and indirect coupling via another component orelement where, for indirect coupling, the intervening component orelement does not modify the operation. Inferred coupling, for examplewhere one element is coupled to another element by inference, includesdirect and indirect coupling between two elements in the same manner as“coupled”.

The illustrative pictorial diagrams depict structures and processactions in a manufacturing process. Although the particular examplesillustrate specific structures and process acts, many alternativeimplementations are possible and commonly made by simple design choice.Manufacturing actions may be executed in different order from thespecific description herein, based on considerations of function,purpose, conformance to standard, legacy structure, and the like.

While the present disclosure describes various embodiments, theseembodiments are to be understood as illustrative and do not limit theclaim scope. Many variations, modifications, additions and improvementsof the described embodiments are possible. For example, those havingordinary skill in the art will readily implement the steps necessary toprovide the structures and methods disclosed herein, and will understandthat the process parameters, materials, shapes, and dimensions are givenby way of example only. The parameters, materials, and dimensions can bevaried to achieve the desired structure as well as modifications, whichare within the scope of the claims. Variations and modifications of theembodiments disclosed herein may also be made while remaining within thescope of the following claims.

What is claimed is:
 1. An electronic device comprising: an inputinterface operable to receive a plurality of taint indicatorscorresponding to at least one of a plurality of taints injected from atleast one of a plurality of resources; at least one taint vectorincluding a plurality of vector fields operable upon one or moreinstructions in parallel to track at least one taint of the plurality oftaints; and a hardware component coupled to the input interface andoperable to track the plurality of taints.
 2. The electronic deviceaccording to claim 1 wherein: the input interface is operable to receiveat least one taint indicator from a tagged system call associated withaccessing information from a web page wherein an operating systeminjects a label originating from a browser at an identified site.
 3. Theelectronic device according to claim 1 wherein: the hardware componentis operable to inject at least one taint of the plurality of taints whenthe at least one taint is known a priori to indicate an event and/orcondition is suspected of at least one of propagating unsafe data ordata received from an unsafe source.
 4. The electronic device accordingto claim 1 further comprising: monitoring logic operable to monitor theat least one taint vector and detect a predetermined taint conditionwherein a predetermined condition of data is indicated.
 5. Theelectronic device according to claim 1 further comprising: monitoringlogic operable to increment the at least one taint vector upon detectionof a predetermined taint condition wherein a predetermined condition ofdata is indicated.
 6. The electronic device according to claim 1 furthercomprising: at least one taint vector including a plurality of vectorfields operable one or more instructions in parallel to list at leastone taint of a plurality of taints indicative of potential security riskof at least one of potentially unsafe data or data received from apotentially unsafe source originating from at least one of the pluralityof resources; and response logic operable to respond to a predeterminedtaint condition.
 7. The electronic device according to claim 1 furthercomprising: monitoring logic operable to monitor taints and create atrust profile based on the monitoring; and response logic operable totrap to a software process based at least partly on determination of asuspicious condition.
 8. The electronic device according to claim 1further comprising: monitoring logic operable to monitor taints innetwork input/output operations; and response logic operable to trap toa software process based at least partly on determination of a networkinput/output condition of an attempt of malware to communicate to amalware operator.
 9. The electronic device according to claim 1 furthercomprising: monitoring logic operable to monitor taints using a hardwaredevice; and response logic operable to insert initial taintnotifications using a software process.
 10. The electronic deviceaccording to claim 1 further comprising: response logic operable torespond to at least one security risk event with at least one of:ignoring the at least one security risk event; logging the at least onesecurity risk event; displaying a notification; displaying a warningmessage; generating an alarm; preventing a memory and/or register write;modifying operating frequency; modifying operating voltage; modifying anoperating parameter; performing a system call; calling a trap and/orexception; terminating operation of selected resources; or activating asystem shutdown.
 11. The electronic device according to claim 1 furthercomprising: monitoring logic operable to accumulate the plurality oftaint indicators independently using at least one of: comparing one ormore of the accumulated plurality of taint indicators to at least onepredetermined threshold; performing power law analysis; performing arace function; counting a number of taints; counting a number of taintsper memory unit; counting a number of instructions tainted; counting anumber of tainted instructions; counting a number of instructionswritten as a result of a taint; counting a number of data loads andstores; counting a number of memory accesses; counting a number ofcalls; counting a number of returns; counting a number of branches;counting a number of integer overflows; counting a number of networkinput/output events; counting a number of null pointer references;counting a number of buffer overruns/overflows; or counting a number ofrepeated attempts to access a key.
 12. The electronic device accordingto claim 1 further comprising: monitoring logic operable to allocatetaints at a selected granularity via at least one of: allocating taintsby memory page; allocating taints by byte; allocating taints by word;allocating taints by memory block; allocating taints by hardware processidentifier (PID); allocating taints to enable a cross-thread taint;allocating taints among hardware devices; allocating taints bycomponent; or allocating taints by software component.
 13. Theelectronic device according to claim 1 further comprising: monitoringlogic operable to acquire and monitor a history of the one or more ofthe at least one taint vector in a feedback loop that correlates taintswith responses to the taints.
 14. The electronic device according toclaim 1 further comprising: monitoring logic operable to apply at leastone function to at least one entry of the at least one taint vector. 15.The electronic device according to claim 14 wherein: the at least onefunction includes at least one of weights, masks, sums, combinations,arithmetic functions, logical operations, or transforms.
 16. Theelectronic device according to claim 1 wherein at least one of theplurality of taints includes at least one of: a null pointer reference;an attempt to access a secured part of a processor; an attempt to accessa secured resource; a buffer overrun; an event originating in a regionthat raises suspicion; a fault; an integer overflow; a plurality oftaint indicators that exceeds at least one predetermined threshold; ataint indicated by power law analysis; a taint indicated by a racefunction; an attempt to access a key; or information indicating aprivacy violation.
 17. The electronic device according to claim 1wherein: the plurality of taints comprise one or more of a plurality ofdistinct classes comprising a plurality of distinct affiliates, systemcharacteristics, sources, events, activities, or conditions.
 18. Theelectronic device according to claim 1 wherein the plurality of taintsare injected by one or more of the plurality of resources including oneor more of physical and/or logical instances of: processors, centralprocessing units (CPUs), graphics hardware, network controllers, memory,memory management, hardware, microarchitecture, sound cards, videocards, network interfaces, instruction set architecture (ISA), librarycalls, library functions, software objects, compilers, or operatingsystems.
 19. The electronic device according to claim 1 wherein: one ormore of the plurality of taints are injected by a resource of theplurality of resources that is remote from the electronic device and atleast one taint indicator corresponding to the injected one or more ofthe plurality of taints is communicated to the electronic device. 20.The electronic device according to claim 1 wherein: one or more of theplurality of taints are injected by remote software that is remote fromthe electronic device and at least one taint indicator corresponding tothe injected one or more of the plurality of taints is communicated tothe electronic device.
 21. The electronic device according to claim 1wherein: one or more of the plurality of taints are injected by aresource of the plurality of resources that is locally coupled to theelectronic device and at least one taint indicator corresponding to theinjected one or more of the plurality of taints is directly accessed bythe electronic device.
 22. The electronic device according to claim 1wherein: one or more of the plurality of taints are injected by localsoftware that is local to the electronic device and at least one taintindicator corresponding to the injected one or more of the plurality oftaints is directly accessed by the electronic device.
 23. The electronicdevice according to claim 1 wherein: one or more of the at least onetaint vector are operable as an accumulator of a plurality of taintindicators indicative of potential security risk of at least one ofpotentially unsafe data or data received from a potentially unsafesource from a plurality of distinct sources at distinct times.
 24. Theelectronic device according to claim 1 wherein: one or more of the atleast one taint vector comprises an entry that is allocated to selectedone or more of the plurality of resources, wherein one or more taints ofthe selected one or more of the plurality of resources are federated tothe entry.
 25. The electronic device according to claim 1 wherein: oneor more of the at least one taint vector comprises a composite taintvector that correlates a taint source and a taint activity type.
 26. Amethod operable in a computing device for handling security riskcomprising: receiving a plurality of taint indicators corresponding toat least one of a plurality of taints injected from at least one of aplurality of resources; executing one or more instructions that operateupon at least one taint vector including a plurality of vector fields;operating upon the plurality of vector fields of the at least one taintvector in parallel using the one or more instructions; and tracking atleast one taint of the plurality of taints.
 27. The method according toclaim 26 further comprising: receiving at least one taint indicator froma tagged system call associated with accessing information from a webpage wherein an operating system injects a label originating from abrowser at an identified site.
 28. The method according to claim 26further comprising: injecting at a hardware component at least one taintof the plurality of taints when the at least one taint is known a priorito indicate an event and/or condition is suspicious.
 29. The methodaccording to claim 26 further comprising: indicating potential securityrisk originating from at least one of the plurality of resources by atleast one taint of the plurality of taints; allocating the at least onetaint of the plurality of taints in the at least one taint vector;monitoring the at least one taint vector; and detecting a predeterminedtaint condition wherein a predetermined condition of data is indicated.30. The method according to claim 26 further comprising: indicatingpotential security risk originating from at least one of the pluralityof resources by at least one taint of the plurality of taints;allocating the at least one taint of the plurality of taints in the atleast one taint vector; and incrementing the at least one taint vectorupon detection of a predetermined taint condition wherein apredetermined condition of data is indicated.
 31. The method accordingto claim 26 further comprising: indicating potential security riskoriginating from at least one of the plurality of resources by at leastone taint of the plurality of taints; listing the at least one taint ofthe plurality of taints in the at least one taint vector; and respondingto a predetermined taint condition.
 32. The method according to claim 26further comprising: monitoring at least one of the plurality of taints;creating a trust profile based on the monitoring; and trapping to asoftware process based at least partly on determination of a suspiciouscondition.
 33. The method according to claim 26 further comprising:monitoring at least one of the plurality of taints in one or morenetwork input/output operations; and trapping to a software processbased at least partly on determination of a network input/outputcondition of an attempt of malware to communicate to a malware operator.34. The method according to claim 26 further comprising: monitoring atleast one of the plurality of taints using a hardware device; andinserting one or more initial taint notifications using a softwareprocess.
 35. The method according to claim 26 further comprising:responding to at least one security risk event with at least one of:ignoring the at least one security risk event; logging the at least onesecurity risk event; displaying a notification; displaying a warningmessage; generating an alarm; preventing a memory and/or register write;modifying operating frequency; modifying operating voltage; modifying anoperating parameter; performing a system call; calling a trap and/orexception; terminating operation of selected resources; or activating asystem shutdown.
 36. The method according to claim 26 furthercomprising: accumulating the plurality of taint indicators independentlyusing at least one of: comparing one or more of the accumulatedplurality of taint indicators to at least one predetermined threshold;performing power law analysis; performing a race function; counting anumber of taints; counting a number of taints per memory unit; countinga number of instructions tainted; counting a number of taintedinstructions; counting a number of instructions written as a result of ataint; counting a number of data loads and stores; counting a number ofmemory accesses; counting a number of calls; counting a number ofreturns; counting a number of branches; counting a number of integeroverflows; counting a number of network input/output events; counting anumber of null pointer references; counting a number of bufferoverruns/overflows; or counting a number of repeated attempts to accessa key.
 37. A computing system comprising: means for receiving aplurality of taint indicators corresponding to at least one of aplurality of taints injected from at least one of a plurality ofresources; means for executing one or more instructions that operateupon at least one taint vector including a plurality of vector fields;means for operating upon the plurality of vector fields of the at leastone taint vector in parallel using the one or more instructions; andmeans for tracking one or more of the plurality of taints.
 38. Theelectronic device according to claim 1 wherein the hardware componentcomprises: at least one timer register configured to change at apredetermined rate; and at least one accumulator configured to update ina predetermined manner in response to receipt of the one or more of theplurality of taint indicators and in response to a predeterminedcondition of the at least one timer register.
 39. The electronic deviceaccording to claim 1 wherein the hardware component comprises: at leastone accumulator configured into a plurality of portions that updateindependently according to distinct accumulation functions in responseto receipt of the one or more of the plurality of taint indicatorscorresponding selectively to distinct taint conditions and sources. 40.The electronic device according to claim 1 wherein the hardwarecomponent comprises: hardware threading circuitry configured for atleast one of simultaneous multithreading (SMT) or hyperthreadingoperating upon the plurality of vector fields of the at least one taintvector in parallel using the one or more instructions; and at least oneaccumulator configured into a plurality of portions that updateindependently according to distinct accumulation functions in responseto receipt of the one or more of the plurality of taint indicatorscorresponding selectively to distinct threads executing on the hardwarethreading circuitry.
 41. The electronic device according to claim 1further comprising: a processor coupled to the input interface andincluding at least the hardware component, the processor operable toexecute one or more instructions in an instruction set architectureconfigured for at least one of simultaneous multithreading (SMT) orhyperthreading operating upon the plurality of vector fields of the atleast one taint vector in parallel using the one or more instructionsincluded in the instruction set architecture.
 42. The electronic deviceaccording to claim 1 further comprising: a processor coupled to theinput interface and including at least the hardware component, theprocessor operable to execute one or more instructions in an instructionset architecture configured for hardware execution of one or morethreads concurrently for at least one of simultaneous multithreading(SMT) or hyperthreading operating upon the plurality of vector fields ofthe at least one taint vector in parallel using the one or moreinstructions included in the instruction set architecture.
 43. Theelectronic device according to claim 1 further comprising: a processorcoupled to the input interface and including at least the hardwarecomponent, the processor configured to execute the one or moreinstructions that operate upon the plurality of vector fields in the atleast one taint vector in parallel to execute a thread hierarchyincluding a currently running list of threads and a pool of non-runningthreads, at least one of the plurality of vector fields operable toreceive computational limit information for at least one of theplurality of resources.
 44. The electronic device according to claim 1further comprising: a processor coupled to the input interface andincluding at least the hardware component, the processor configured toexecute the one or more instructions that operate upon the plurality ofvector fields in the at least one taint vector in parallel to setcomputational limits for at least one of a plurality of resources basedat least in part on a priority level indicative of resource availabilityspecified in at least one of the plurality of vector fields operable toreceive computational limit information.
 45. The electronic deviceaccording to claim 1 further comprising: a processor coupled to theinput interface and including at least the hardware component, theprocessor configured to execute the one or more instructions thatoperate upon the plurality of vector fields in the at least one taintvector in parallel to set computational limits for at least one of aplurality of resources based at least in part on a user-specifiedoverride configured to override computational limit information receivedfrom at least one of the plurality of resources, the user-specifiedoverride specified in at least one of the plurality of vector fieldsoperable to receive computational limit information.